AD9540 Low Jitter, DDS-based Clock Generator and Synthesizer

Applications Clocking high performance data converters Basestation clocking applications Network (SONET/SDH) clocking Gigabit Ethernet (GbE) clocking Instrumentation clocking circuits

The AD9540 supports a variety of functions including signal synthesis and low jitter clock generation useful in a wide variety of applications. The device features high performance PLL circuitry including a flexible 200 MHz Phase Frequency Detector and a digitally controlled charge pump current. The device also provides a low jitter, 655 MHz CML mode (PECL compatible) output driver with programmable slew rates. External VCO rates up to 2.7 GHz are supported. An onboard 400 MSPS DDS provides extremely fine tuning resolution and phase programmability. Information is loaded into the AD9540 via a serial I/O port which has a device write speed of 25Mbit/sec. The AD9540 frequency divider block can also be programmed to support a spread spectrum clocking mode.

The AD9540 is specified to operate over the extended automotive range of -40°C to +85°C.

Applications
  • Clocking high performance data converters
  • Basestation clocking applications
  • Network (SONET/SDH) clocking
  • Gigabit Ethernet (GbE) clocking
  • Instrumentation clocking circuits
Features and Benefits
  • Intrinsic Jitter performance < 500 fs
  • Synthesizes signals to 2.7 GHz
  • Generates clock signals to 655 MHz
  • 25 Mbit/sec write speed
    Serial I/O Control
  • 200 MHz Phase Frequency Detector Inputs
  • 400 MSPS DDS onboard
    Programmable edge delay w/
    93 fs resolution
    Frequency resolution <2.33 µHz
  • 655 MHz Programmable Input Dividers for the Phase Frequency Detector (÷M,N) {M,N =1..16} (bypassable)
  • 8 Programmable internal clock rates
  • 1.8 V Supply for device operation
    3.3 V Supply for I/O, CML Driver &
    Charge Pump Output
  • Software controlled power-down
  • 48-lead LFCSP package
  • Programmable charge pump current (up to 4 mA)
Clock & Timing
RF & Microwave
Data Sheets
Documentnote
AD9540:  655 MHz Low Jitter Clock Generator Data Sheet (Rev. A)PDF 839 kB
Application Notes
Documentnote
AN-1389: Recommended Rework Procedure for the Lead Frame Chip Scale Package (LFCSP) (Rev. 0)PDF 133.7 K
AN-501: Aperture Uncertainty and ADC System Performance (Rev. A)PDF 227 kB
AN-756: Sampled Systems and the Effects of Clock Phase Noise and Jitter (Rev. 0)PDF 291.7 K
AN-769: Generating Multiple Clock Outputs from the AD9540 (Rev. 0)PDF 0
AN-939: Super-Nyquist Operation of the AD9912 Yields a High RF Output Signal (Rev. 0)PDF 221 kB
AN-837: DDS-Based Clock Jitter Performance vs. DAC Reconstruction Filter Performance (Rev. 0)PDF 313 kB
AN-621: Programming the AD9832/AD9835PDF 202 kB
AN-557: An Experimenter's Project: (Rev. 0)PDF 368 kB
AN-419: A Discrete, Low Phase Noise, 125 MHz Crystal Oscillator for the AD9850PDF 101 kB
AN-237: Choosing DACs for Direct Digital SynthesisPDF 1156 kB
AN-423: Amplitude Modulation of the AD9850 Direct Digital SynthesizerPDF 37 kB
AN-345: Grounding for Low-and-High-Frequency CircuitsPDF 455 kB
AN-342: Analog Signal-Handling for High Speed and AccuracyPDF 468 kB
AN-823: Direct Digital Synthesizers in Clocking Applications Time (Rev. 0)PDF 115 kB
AN-280: Mixed Signal Circuit TechnologiesPDF 2101 kB
AN-605: Synchronizing Multiple AD9852 DDS-Based Synthesizers (Rev. 0)PDF 527 kB
AN-927: Determining if a Spur is Related to the DDS/DAC or to Some Other Source (For Example, Switching Supplies) (Rev. 0)PDF 170 kB
AN-587: Synchronizing Multiple AD9850/AD9851 DDS-Based Synthesizers (Rev. 0)PDF 116 kB
AN-953: Direct Digital Synthesis (DDS) with a Programmable Modulus (Rev. B)PDF 112 kB
AN-772: A Design and Manufacturing Guide for the Lead Frame Chip Scale Package (LFCSP) (Rev. 0)PDF 439 kB
AN-873: Lock Detect on the ADF4xxx Family of PLL Synthesizers (Rev. 0)PDF 207 kB
AN-851: A WiMax Double Downconversion IF Sampling Receiver Design (Rev. 0)PDF 262 kB
AN-741: Little Known Characteristics of Phase Noise (Rev. 0)PDF 1679 kB
AN-632: Provisionary Data Rates Using the AD9951 DDS as an Agile Reference Clock for the ADN2812 Continuous-Rate CDR (Rev. 0)PDF 138 kB
AN-543: High Quality, All-Digital RF Frequency Modulation Generation with the ADSP-2181 and the AD9850 DDS
AN-543 - Monaural FM Transmitter AN-543 - Stereo FM Transmitter		PDF 49.25 K
Product Highlight
Documentnote
Introducing Digital Up/Down Converters: VersaCOMM™ Reconfigurable Digital ConvertersPDF 63 kB
Frequently Asked Questions
Documentnote
Order Information
Part NumberPackagePacking QtyTemp RangePrice 100-499Price 1000+RoHS
AD9540BCPZ Production48 ld LFCSP (7x7x.85mm w/5.1mm Pad) OTH 260-40 to 85C15.3913.09Y
AD9540BCPZ-REEL7 Production48 ld LFCSP (7x7x.85mm w/5.1mm Pad) REEL 750-40 to 85C15.3913.09Y
Reference Materials
AD9540:  655 MHz Low Jitter Clock Generator Data Sheet (Rev. A) ad9540
AN-1389: 引线框芯片级封装(LFCSP)的建议返修程序 (Rev. 0) ad9540
AN-1389: Recommended Rework Procedure for the Lead Frame Chip Scale Package (LFCSP) (Rev. 0) ad9856
AN-501: Aperture Uncertainty and ADC System Performance (Rev. A) ad9220
AN-756: Sampled Systems and the Effects of Clock Phase Noise and Jitter (Rev. 0) ad9220
AN-769: Generating Multiple Clock Outputs from the AD9540 (Rev. 0) ad9540
AN-939: Super-Nyquist Operation of the AD9912 Yields a High RF Output Signal (Rev. 0) ad9540
AN-837: DDS-Based Clock Jitter Performance vs. DAC Reconstruction Filter Performance (Rev. 0) ad9856
AN-621: Programming the AD9832/AD9835 ad9540
AN-557: An Experimenter's Project: (Rev. 0) ad9540
AN-419: A Discrete, Low Phase Noise, 125 MHz Crystal Oscillator for the AD9850 ad9540
AN-237: Choosing DACs for Direct Digital Synthesis ad9856
AN-423: Amplitude Modulation of the AD9850 Direct Digital Synthesizer ad9540
AN-345: Grounding for Low-and-High-Frequency Circuits ad9220
AN-342: Analog Signal-Handling for High Speed and Accuracy ad1674
AN-823: Direct Digital Synthesizers in Clocking Applications Time (Rev. 0) ad9856
AN-280: Mixed Signal Circuit Technologies ad1674
AN-605: Synchronizing Multiple AD9852 DDS-Based Synthesizers (Rev. 0) ad9540
AN-927: Determining if a Spur is Related to the DDS/DAC or to Some Other Source (For Example, Switching Supplies) (Rev. 0) ad9540
AN-587: Synchronizing Multiple AD9850/AD9851 DDS-Based Synthesizers (Rev. 0) ad9540
AN-772: 引脚架构芯片级封装（LFCSP）设计与制造指南 (Rev. 0) ad9540
AN-769: 基于AD9540产生多时钟输出 (Rev. 0) ad9540
AN-237: 放大器直接数字频率合成的DAC选型器应用漫谈 (Rev. 0) ad9540
AN-953: 具可编程模数的直接数字频率合成器(DDS) (Rev. 0) ad9540
AN-873: ADF4xxx系列PLL频率合成器的锁定检测 (Rev. 0) ad9540
AN-605: 同步多个基于DDS的频率合成器AD9852 (Rev. A) ad9540
AN-953: Direct Digital Synthesis (DDS) with a Programmable Modulus (Rev. B) ad9540
AN-939: 利用AD9912的超奈奎斯特频率操作得到高RF输出信号 (Rev. 0) ad9540
AN-927: 确定杂散来源是DDS/DAC还是其他器件(例如开关电源)[中文版] (Rev. 0) ad9540
AN-837: 基于DDS的时钟抖动性能与DAC重构滤波器性能的关系[中文版] (Rev. 0) ad9540
AN-772: A Design and Manufacturing Guide for the Lead Frame Chip Scale Package (LFCSP) (Rev. 0) ad9856
AN-873: Lock Detect on the ADF4xxx Family of PLL Synthesizers (Rev. 0) ad9540
AN-823: 时钟应用中的直接数字频率合成器[中文版] (Rev. 0) ad9540
AN-851: 一种WiMax双下变频IF采样接收机设计方案[中文版] (Rev. 0) ad9540
AN-851: A WiMax Double Downconversion IF Sampling Receiver Design (Rev. 0) ad9856
AN-345: 低频和高频电路接地 ad9540
AN-756: 系统采样以及时钟相位噪声和抖动的影响[中文版] (Rev. 0) ad9540
AN-501: 孔径不确定度与ADC系统性能[中文版] (Rev. A) ad9540
AN-741: Little Known Characteristics of Phase Noise (Rev. 0) ad9221
AN-741: 鲜为人知的相位噪声特性 ad9540
AN-632: 利用AD9951 DDS作为ADN2812连续速率CDR的捷变参考时钟以提供数据速率 (Rev. 0) ad9540
AN-632: Provisionary Data Rates Using the AD9951 DDS as an Agile Reference Clock for the ADN2812 Continuous-Rate CDR (Rev. 0) ad9540
AN-621: AD9832/AD9835的编程 (Rev. 0) ad9540
AN-342: 高速、高精度处理模拟信号[中文版] (Rev. 0) ad9540
AN-557: 实验者项目： (Rev. 0) ad9540
AN-419: 用于完整的直接数字频率合成器AD9850的分立、低相位噪声、125MH晶振 (Rev. A) ad9540
AN-423: 直接数字频率合成器AD9850的幅度调制 (Rev. A) ad9540
AN-587: 同步多个基于DDS的频率合成器AD9850/AD9851 (Rev. 0) ad9540
AN-543: 利用ADSP-2181 DSP和AD9850直接数字频率合成器产生高质量、全数字RF频率调制 (Rev. A) ad9540
AN-543 - Monaural FM Transmitter ad9540
AN-543: High Quality, All-Digital RF Frequency Modulation Generation with the ADSP-2181 and the AD9850 DDS ad9540
AN-543 - Monaural FM Transmitter ad9540
Introducing Digital Up/Down Converters: VersaCOMM™ Reconfigurable Digital Converters ad9856
Basics of Designing a Digital Radio Receiver (Radio 101) ad9856
Digital Up/Down Converters: VersaCOMM™ White Paper ad9856
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