AD9572 Fiber Channel/Ethernet Clock Generator IC, PLL Core, Dividers, 7 Clock Outputs

The AD9572 provides a multioutput clock generator function along with two on-chip PLL cores, optimized for fiber channel line card applications that include an Ethernet interface. The integer-N PLL design is based on the Analog Devices, Inc., proven portfolio of high performance, low jitter frequencysynthesizers to maximize network performance. Other applications with demanding phase noise and jitter requirements also benefit from this part. APPLICATIONS Fiber channel line cards, switches, and routers Gigabit Ethernet/PCIe support included Low jitter, low phase noise clock generation

The PLL section consists of a low noise phase frequency detector (PFD), a precision charge pump (CP), a low phase noise voltage controlled oscillator (VCO), and a preprogrammed feedback divider and output divider. By connecting an external crystal or reference clock to the REFCLK pin, frequencies up to 156.25 MHz can be locked to the input reference. Each output divider and feedback divider ratio is preprogrammed for the required output rates.

A second PLL also operates as an integer-N synthesizer and drives two LVPECL or LVDS output buffers for 106.25 MHz operation. No external loop filter components are required, thus conserving valuable design time and board space.

The AD9572 is available in a 40-lead, 6 mm × 6 mm lead frame chip scale package (LFCSP) and can be operated from a single 3.3 V supply. The temperature range is −40°C to +85°C.

Features and Benefits

Fully integrated dual VCO/PLL cores
167 fs rms jitter from 0.637 MHz to 10 MHz
at 106.25 MHz
178 fs rms jitter from 1.875 MHz to 20 MHz
at 156.25 MHz

418 fs rms jitter from 12 kHz to 20 MHz
at 125 MHz Input crystal or clock frequency of 25 MHz

Preset divide ratios for 106.25 MHz, 156.25 MHz, 33.33 MHz, 100 MHz, 125 MHz

Choice of LVPECL or LVDS output format

Integrated loop filters

Copy of reference clock output

Rates configured via strapping pins

Space saving, 6 mm × 6 mm, 40-lead LFCSP

0.71 W power dissipation (LVDS operation)

1.07 W power dissipation (LVPECL operation)

3.3 V operation

Data Sheets

Document	note
AD9572: Fiber Channel/Ethernet Clock Generator IC, PLL Core, Dividers, 7 Clock Outputs Data Sheet (Rev. B)	PDF 415 kB

Frequently Asked Questions

Document	note

Order Information

Part Number	Package	Packing Qty	Temp Range	Price 100-499	Price 1000+	RoHS
AD9572ACPZLVD Production	40 ld LFCSP (6x6mm w/4.6mm pad)	OTH 490	-40 to 85C	6	5.1	Y
AD9572ACPZLVD-R7 Production	40 ld LFCSP (6x6mm w/4.6mm pad)	REEL 750	-40 to 85C	6	5.1	Y
AD9572ACPZLVD-RL Production	40 ld LFCSP (6x6mm w/4.6mm pad)	REEL 2500	-40 to 85C	0	5.1	Y
AD9572ACPZPEC Production	40 ld LFCSP (6x6mm w/4.6mm pad)	OTH 490	-40 to 85C	6	5.1	Y
AD9572ACPZPEC-R7 Production	40 ld LFCSP (6x6mm w/4.6mm pad)	REEL 750	-40 to 85C	6	5.1	Y
AD9572ACPZPEC-RL Production	40 ld LFCSP (6x6mm w/4.6mm pad)	REEL 2500	-40 to 85C	0	5.1	Y

Evaluation Boards

Part Number	Description	Price	RoHS
AD9572-EVALZ-LVD	Evaluation Board	250	Y
AD9572-EVALZ-PEC	Evaluation Board	581.9	Y

AD9572: Fiber Channel/Ethernet Clock Generator IC, PLL Core, Dividers, 7 Clock Outputs Data Sheet (Rev. B) ad9572

AD9571/AD9572 IBIS Model ad9572