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AD9628 12-Bit, 125/105 MSPS, 1.8 V Dual Analog-to-Digital Converter

The AD9628 operates from a single 1.8 V analog power supply and features a separate digital output driver supply to accommodate 1.8 V CMOS or LVDS logic families.  The patented sample-and-hold circuit maintains excellent performance for input frequencies up to 200 MHz and is designed for low cost, low power, and ease of use.  A standard serial port interface supports various product features and functions, such as data output formatting, internal clock divider, power-down, DCO/data timing and offset adjustments.  The AD9628 is packaged in a 64-lead RoHS-compliant LFCSP that is pin compatible with the AD9650/AD9269/ AD9268 16-bit ADC, the AD9258/AD9251/AD9648 14-bit ADCs, the AD9231 12-bit ADC, and the AD9608/AD9204 10-bit ADCs, enabling a simple migration path between 10-bit and 16-bit converters sampling from 20MSPS to 125MSPS.

The AD9628 is a monolithic, dual-channel, 1.8 V supply, 12-bit, 125 MSPS/105 MSPS analog-to-digital converter (ADC). It features a high performance sample-and-hold circuit and on-chip voltage reference.

The product uses multistage differential pipeline architecture with output error correction logic to provide 12-bit accuracy at 125 MSPS data rates and to guarantee no missing codes over the full operating temperature range.

The ADC contains several features designed to maximize flexibility and minimize system cost, such as programmable clock and data alignment and programmable digital test pattern generation. The available digital test patterns include built-in deterministic and pseudorandom patterns, along with custom user-defined test patterns entered via the serial port interface (SPI).

A differential clock input controls all internal conversion cycles. An optional duty cycle stabilizer (DCS) compensates for wide variations in the clock duty cycle while maintaining excellent overall ADC performance.

The digital output data is presented in offset binary, Gray code, or twos complement format. A data output clock (DCO) is provided for each ADC channel to ensure proper latch timing with receiving logic. 1.8 V CMOS or LVDS output logic levels are supported. Output data can also be multiplexed onto a single output bus.

Applications

• Communications
• Diversity radio systems
• Multimode digital receivers
• GSM, EDGE, W-CDMA, LTE, CDMA2000, WIMAX, TD-SCDMA
• I/Q demodulation systems
• Smart antenna systems
• Broadband data applications
• Battery-powered instruments
• Hand-held scope meters
• Portable medical imaging
• Ultrasound
• Radar/LIDAR

Product Highlights

• The AD9628 operates from a single 1.8 V analog power supply and features a separate digital output driver supply to accommodate 1.8 V CMOS or LVDS logic families.
• The patented sample-and-hold circuit maintains excellent performance for input frequencies up to 200 MHz and is designed for low cost, low power, and ease of use.
• A standard serial port interface supports various product features and functions, such as data output formatting, internal clock divider, power-down, DCO/data timing and offset adjustments.
• The AD9628 is packaged in a 64-lead RoHS-compliant LFCSP that is pin compatible with the AD9650/AD9269/ AD9268 16-bit ADC, the AD9258/AD9251/AD9648 14-bit ADCs, the AD9231 12-bit ADC, and the AD9608/AD9204 10-bit ADCs, enabling a simple migration path between 10-bit and 16-bit converters sampling from 20MSPS to 125MSPS.

Data Sheets

Application Notes

User Guides

Order Information

Evaluation Boards

Reference Materials

• Product Selection Guide：RF Source Booklet
• Technical Articles：MS-2210: Designing Power Supplies for High Speed ADC