AD9644 14-Bit, 80 MSPS/155 MSPS, 1.8V Dual, Serial Output A/D Converter

The dual ADC core features a multistage, differential pipelined architecture with integrated output error correction logic. Each ADC features wide bandwidth differential sample-and-hold analog input amplifiers that support a variety of user-selectable input ranges. An integrated voltage reference eases design consid-erations. A duty cycle stabilizer is provided to compensate for variations in the ADC clock duty cycle, allowing the converters to maintain excellent performance. By default, the ADC output data is routed directly to the two external JESD204A serial output ports. These outputs are at CML voltage levels. Two modes are supported such that output coded data is either sent through one data link or two. (L = 1; F = 4 or L = 2; F = 2). Independent synchronization inputs (DSYNC) are provided for each channel. Flexible power-down options allow significant power savings, when desired. Programming for setup and control is accomplished using a 3-wire SPI-compatible serial interface. The AD9644 is available in a 48-lead LFCSP and is specified over the industrial temperature range of −40°C to +85°C. This product is protected by a U.S. patent. Applications Communications Diversity radio systems Multimode digital receivers (3G and 4G) GSM, EDGE, W-CDMA, LTE, CDMA2000, WiMAX, TD-SCDMA I/Q demodulation systems Smart antenna systems General-purpose software radios Broadband data applications Ultrasound equipment Product Highlights An on-chip PLL allows users to provide a single ADC sampling clock; the PLL multiplies the ADC sampling clock to produce the corresponding data rate clock. The configurable JESD204A output block supports up to 1.6 Gbps per channel data rate when using a dedicated data link per ADC or 3.2 Gbps data rate when using a single shared data link for both ADCs. Proprietary differential input that maintains excellent SNR performance for input frequencies up to 250 MHz. Operation from a single 1.8 V power supply. Standard serial port interface (SPI) that supports various product features and functions, such as data formatting (offset binary, twos complement, or gray coding), enabling the clock DCS, power-down, test modes, voltage reference mode, and serial output configuration.

The AD9644 is a dual, 14-bit, analog-to-digital converter (ADC) with a high speed serial output interface and sampling speeds of either 80 MSPS or 155 MSPS.

The AD9644 is designed to support communications appli-cations where high performance, combined with low cost, small size, and versatility, is desired. The JESD204A high speed serial interface reduces board routing requirements and lowers pin count requirements for the receiving device.

The dual ADC core features a multistage, differential pipelined architecture with integrated output error correction logic. Each ADC features wide bandwidth differential sample-and-hold analog input amplifiers that support a variety of user-selectable input ranges. An integrated voltage reference eases design consid-erations. A duty cycle stabilizer is provided to compensate for variations in the ADC clock duty cycle, allowing the converters to maintain excellent performance.

By default, the ADC output data is routed directly to the two external JESD204A serial output ports. These outputs are at CML voltage levels. Two modes are supported such that output coded data is either sent through one data link or two. (L = 1; F = 4 or L = 2; F = 2). Independent synchronization inputs (DSYNC) are provided for each channel.

Flexible power-down options allow significant power savings, when desired.

Programming for setup and control is accomplished using a 3-wire SPI-compatible serial interface.

The AD9644 is available in a 48-lead LFCSP and is specified over the industrial temperature range of −40°C to +85°C.

This product is protected by a U.S. patent.

Features and Benefits
  • JESD204A coded serial digital outputs
  • SNR = 73.7 dBFS at 70 MHz and 80 MSPS
  • SNR = 71.7 dBFS at 70 MHz and 155 MSPS
  • SFDR = 92 dBc at 70 MHz and 80 MSPS
  • SFDR = 92 dBc at 70 MHz and 155 MSPS
  • Low power: 423 mW at 80 MSPS, 567 mW at 155 MSPS
  • 1.8 V supply operation
  • IF sampling frequencies to 250 MHz
  • Integer 1-to-8 input clock divider
    −148.6 dBFS/Hz input noise at 180 MHz and 80 MSPS
  • -150.3 dBFS/Hz input noise at 180 MHz and 155 MSPS
  • Please see data sheet for additional features
Analog to Digital Converters
IBIS Models
MathWorks®
S-Parameters
Data Sheets
Documentnote
AD9644: 14-Bit, 80 MSPS/155 MSPS, 1.8 V Dual Serial Output Analog-to-Digital Converter (ADC) Data Sheet (Rev. C)PDF 1082 kB
Application Notes
Documentnote
AN-878: High Speed ADC SPI Control Software (Rev. A)PDF 585 kB
AN-827: A Resonant Approach to Interfacing Amplifiers to Switched-Capacitor ADCs (Rev. 0)PDF 203 kB
AN-935: Designing an ADC Transformer-Coupled Front End (Rev. 0)PDF 363 kB
AN-742: Frequency Domain Response of Switched-Capacitor ADCs (Rev. B)PDF 401 kB
AN-586: LVDS Outputs for High Speed A/D Converters (Rev. 0)PDF 207 kB
AN-1142: Techniques for High Speed ADC PCB Layout (Rev. 0)PDF 392 kB
AN-807: Multicarrier WCDMA Feasibility (Rev. 0)PDF 969 kB
AN-808: Multicarrier CDMA2000 Feasibility (Rev. 0)PDF 1535 kB
AN-812: MicroController-Based Serial Port Interface (SPI) Boot Circuit (Rev. 0)
Software Download (zip, 21,702,560 bytes)		PDF 441 kB
User Guides
Documentnote
UG-294: Evaluating the AD9644/AD9641 Analog-to-Digital ConvertersPDF 4934 kB
Order Information
Part NumberPackagePacking QtyTemp RangePrice 100-499Price 1000+RoHS
AD9644BCPZ-155 Production48 ld LFCSP (7x7x.85 w/5.5mm EP)OTH 260-40 to 85C7563.75Y
AD9644BCPZ-80 Production48 ld LFCSP (7x7x.85 w/5.5mm EP)OTH 260-40 to 85C4941.65Y
AD9644BCPZRL7-155 Production48 ld LFCSP (7x7x.85 w/5.5mm EP)REEL 750-40 to 85C7563.75Y
AD9644BCPZRL7-80 Production48 ld LFCSP (7x7x.85 w/5.5mm EP)REEL 750-40 to 85C041.65Y
AD9644CCPZ-80 Production48 ld LFCSP (7x7x.85 w/5.5mm EP)OTH 260-40 to 85C44.1137.5Y
AD9644CCPZRL7-80 Production48 ld LFCSP (7x7x.85 w/5.5mm EP)REEL 750-40 to 85C037.5Y
Evaluation Boards
Part NumberDescriptionPriceRoHS
AD9644-155KITZEvaluation Board900Y
AD9644-80KITZEvaluation Board900Y
Reference Materials
AD9644: 14-Bit, 80 MSPS/155 MSPS, 1.8 V Dual Serial Output Analog-to-Digital Converter (ADC) Data Sheet (Rev. C) ad9644
AD9644 IBIS Model ad9644
AD9641/AD9644-155 S-Parameter Data ad9644
AD9641/AD9644 S参数数据 ad9644
AN-878: High Speed ADC SPI Control Software (Rev. A) ad6655
AN-808: CDMA2000多载波系统可行性研究 (Rev. 0) adl5330
AN-827: A Resonant Approach to Interfacing Amplifiers to Switched-Capacitor ADCs (Rev. 0) ad6655
AN-935: Designing an ADC Transformer-Coupled Front End (Rev. 0) ad9220
AN-742: Frequency Domain Response of Switched-Capacitor ADCs (Rev. B) ad7476
AN-586: LVDS Outputs for High Speed A/D Converters (Rev. 0) ad6642
AN-1142: 高速ADC PCB布局布线技巧 (Rev. 0) ad6655
AN-1142: Techniques for High Speed ADC PCB Layout (Rev. 0) ad6655
AN-878: 高速ADC SPI控制软件[中文版] (Rev. A) ad6655
AN-807: 多载波WCDMA的可行性 (Rev. 0) adf4106
AN-807: Multicarrier WCDMA Feasibility (Rev. 0) ad6655
AN-808: Multicarrier CDMA2000 Feasibility (Rev. 0) ad9863
AN-827: 放大器与开关电容ADC接口的匹配方法[中文版] (Rev. 0) ad8351
AN-935: ADC变压器耦合前端设计[中文版] (Rev. 0) ad6655
AN-586: 高速模数转换器的LVDS数据输出[中文版] (Rev. 0) ad6642
AN-812: 基于微控制器的串行端口接口(SPI®)启动电路 (Rev. 0) adg3304
AN-812: MicroController-Based Serial Port Interface (SPI) Boot Circuit (Rev. 0) ad6655
Software Download (zip, 21,702,560 bytes) ad6655
UG-294: Evaluating the AD9644/AD9641 Analog-to-Digital Converters ad9644
MS-2210：高速ADC的电源设计 ad9861
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