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AD9649 14-Bit, 20/40/65/80 MSPS, 1.8 V Analog-to-Digital Converter

The ADC contains several features designed to maximize flexibility and minimize system cost, such as programmable clock and data alignment and programmable digital test pattern generation. The available digital test patterns include built-in deterministic and pseudorandom patterns, along with custom user-defined test patterns entered via the serial port interface (SPI). A differential clock input with optional 1, 2, or 4 divide ratios controls all internal conversion cycles. The digital output data is presented in offset binary, gray code, or twos complement format. A data output clock (DCO) is provided to ensure proper latch timing with receiving logic. Both 1.8 V and 3.3 V CMOS levels are supported. The AD9649 is available in a 32-lead RoHS-compliant LFCSP and is specified over the industrial temperature range (−40°C to +85°C). Applications Communications Diversity radio systems Multimode digital receivers GSM, EDGE, W-CDMA, LTE, CDMA2000, WiMAX, TD-SCDMA Smart antenna systems Battery-powered instruments Handheld scope meters Portable medical imaging Ultrasound Radar/LIDAR Product Highlights The AD9649 operates from a single 1.8 V analog power supply and features a separate digital output driver supply to accommodate 1.8 V to 3.3 V logic families. The patented sample-and-hold circuit maintains excellent performance for input frequencies up to 200 MHz and is designed for low cost, low power, and ease of use. A standard serial port interface (SPI) supports various product features and functions, such as data output format-ting, internal clock divider, power-down, DCO, data output (D13 to D0) timing and offset adjustments, and voltage reference modes. The AD9649 is packaged in a 32-lead RoHS-compliant LFCSP that is pin compatible with the AD9629 12-bit ADC and the AD9609 10-bit ADC, enabling a simple migration path between 10-bit and 14-bit converters sampling from 20 MSPS to 80 MSPS.

The AD9649 is a monolithic, single channel 1.8 V supply, 14-bit, 20/40/65/80 MSPS analog-to-digital converter (ADC). It features a high performance sample-and-hold circuit and an on-chip volt-age reference.

The product uses multistage differential pipeline architecture with output error correction logic to provide 14-bit accuracy at 80 MSPS data rates and to guarantee no missing codes over the full operating temperature range.

The ADC contains several features designed to maximize flexibility and minimize system cost, such as programmable clock and data alignment and programmable digital test pattern generation. The available digital test patterns include built-in deterministic and pseudorandom patterns, along with custom user-defined test patterns entered via the serial port interface (SPI).

A differential clock input with optional 1, 2, or 4 divide ratios controls all internal conversion cycles.

The digital output data is presented in offset binary, gray code, or twos complement format. A data output clock (DCO) is provided to ensure proper latch timing with receiving logic. Both 1.8 V and 3.3 V CMOS levels are supported.

The AD9649 is available in a 32-lead RoHS-compliant LFCSP and is specified over the industrial temperature range (−40°C to +85°C).

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Reference Materials

• Solutions Bulletins & Brochures：Analog-to-Digital Converter and Drivers ICs Solutions Bulletin, Volume 10,...
• Technical Articles：MS-2210: Designing Power Supplies for High Speed ADC