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AD9656 Quad, 16-Bit, 125 MSPS JESD204B 1.8 V Analog-to-Digital Converter

Individual-channel power-down is supported and typically consumes less than 2 mW when all channels are disabled. The ADC contains several features designed to maximize flexibility and minimize system cost, such as programmable output clock and data alignment and digital test pattern generation. The available digital test patterns include built-in deterministic and pseudorandom patterns, along with custom user-defined test patterns entered via the serial port interface (SPI). The AD9656 is available in a RoHS-compliant, 56-lead LFCSP. It is specified over the industrial temperature range of −40°C to +85°C. PRODUCT HIGHLIGHTS It has a small footprint. Four ADCs are contained in a small, 8 mm × 8 mm package. An on-chip phase-locked loop (PLL) allows users to providea single ADC sampling clock; the PLL multiplies the ADCsampling clock to produce the corresponding JESD204Bdata rate clock The configurable JESD204B output block supports up to 6.4 Gbps per lane. JESD204B output block supports one, two, and four laneconfigurations. Low power of 198 mW per channel at 125 MSPS, two lanes. The SPI control offers a wide range of flexible features to meet specific system requirements.. APPLICATIONS Medical imaging High speed imaging Quadrature radio receivers Diversity radio receivers Portable test equipment

The AD9656 is a quad, 16-bit, 125 MSPS analog-to-digital converter (ADC) with an on-chip sample-and-hold circuit designed for low cost, low power, small size, and ease of use. The product operates at a conversion rate of up to 125 MSPS and is optimized for outstanding dynamic performance and low power in applications where a small package size is critical.

The ADC requires a single 1.8 V power supply and LVPECL-/ CMOS-/LVDS-compatible sample rate clock for full performance operation. No external reference or driver components are required for many applications.

Individual-channel power-down is supported and typically consumes less than 2 mW when all channels are disabled. The ADC contains several features designed to maximize flexibility and minimize system cost, such as programmable output clock and data alignment and digital test pattern generation. The available digital test patterns include built-in deterministic and pseudorandom patterns, along with custom user-defined test patterns entered via the serial port interface (SPI).

The AD9656 is available in a RoHS-compliant, 56-lead LFCSP.

It is specified over the industrial temperature range of −40°C to +85°C.

PRODUCT HIGHLIGHTS

• It has a small footprint. Four ADCs are contained in a small, 8 mm × 8 mm package.
• An on-chip phase-locked loop (PLL) allows users to providea single ADC sampling clock; the PLL multiplies the ADCsampling clock to produce the corresponding JESD204Bdata rate clock
• The configurable JESD204B output block supports up to 6.4 Gbps per lane.
• JESD204B output block supports one, two, and four laneconfigurations.
• Low power of 198 mW per channel at 125 MSPS, two lanes.
• The SPI control offers a wide range of flexible features to meet specific system requirements..

APPLICATIONS

• Medical imaging
• High speed imaging
• Quadrature radio receivers
• Diversity radio receivers
• Portable test equipment

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