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AD9681 Octal, 14-Bit, 125 MSPS, Serial LVDS, 1.8 V Analog-to-Digital Converter

The AD9681 is an octal, 14-bit, 125 MSPS analog-to-digital converter (ADC) with an on-chip sample-and-hold circuit that is designed for low cost, low power, small size, and ease of use. The device operates at a conversion rate of up to 125 MSPS and is optimized for outstanding dynamic performance and low power in applications where a small package size is critical. Small Footprint. Eight ADCs are contained in a small, 10 mm × 10 mm package. Low Power. The device dissipates 110 mW per channel at 125 MSPS with scalable power options. Ease of Use. Data clock outputs (DCO±1, DCO±2) operate at frequencies of up to 500 MHz and support double data rate (DDR) operation. User Flexibility. SPI control offers a wide range of flexible features to meet specific system requirements.

The ADC requires a single 1.8 V power supply and an LVPECL-/ CMOS-/LVDS-compatible sample rate clock for full performance operation. No external reference or driver components are required for many applications.

The AD9681 automatically multiplies the sample rate clock for the appropriate LVDS serial data rate. Data clock outputs (DCO±1, DCO±2) for capturing data on the output and frame clock outputs (FCO±1, FCO±2) for signaling a new output byte are provided. Individual channel power-down is supported, and the device typically consumes less than 2 mW when all channels are disabled.

The ADC contains several features designed to maximize flexibility and minimize system cost, such as programmable clock and data alignment and programmable digital test pattern generation. The available digital test patterns include built-in deterministic and pseudorandom patterns, along with custom user-defined test patterns entered via the serial port interface (SPI).

The AD9681 is available in an RoHS-compliant, 144-ball CSP-BGA. It is specified over the industrial temperature range of −40°C to +85°C. This product is protected by a U.S. patent.

PRODUCT HIGHLIGHTS

• Small Footprint. Eight ADCs are contained in a small, 10 mm × 10 mm package.
• Low Power. The device dissipates 110 mW per channel at 125 MSPS with scalable power options.
• Ease of Use. Data clock outputs (DCO±1, DCO±2) operate at frequencies of up to 500 MHz and support double data rate (DDR) operation.
• User Flexibility. SPI control offers a wide range of flexible features to meet specific system requirements.

APPLICATIONS

• Medical imaging
• Communications receivers
• Multichannel data acquisition

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