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AD9789 14-Bit, 2400 MSPS RF DAC with 4-Channel Signal Processing

The on-chip rate converter supports a wide range of baud rates with a fixed DAC clock. The digital upconverter can place the channels from 0 to 0.5 × fDAC. This permits four contiguous channels to be synthesized and placed anywhere from dc to fDAC/2. The AD9789 includes a serial peripheral interface (SPI) for device configuration and status register readback. The flexible digital interface can be configured for data bus widths of 4, 8, 16, and 32 bits. It can accept real or complex data. The AD9789 operates from 1.5 V, 1.8 V, and 3.3 V supplies for a total power consumption of 1.6 W. It is supplied in a 164-ball chip scale package ball grid array for lower thermal impedance and reduced package parasitics. No special power sequencing is required. The clock receiver powers up muted to prevent start-up noise. Product Highlights Highly integrated and configurable QAM mappers, interpolators, and upconverters for direct synthesis of 1 to 4 DOCSIS or DVB compatible channels in a block. Low noise and intermodulation distortion (IMD) performance enable high quality synthesis of signals up to 1 GHz. Flexible data interface supports LVDS for outstanding SFDR or CMOS input data for less demanding applications. Interface is configurable from 4-bit nibbles to 32-bit words and can run at up to 150 MHz CMOS or 150 MHz LVDS DDR. Manufactured on a CMOS process, the AD9789 uses a proprietary switching technique that enhances dynamic performance. Applications Broadband communications systems CMTS/DVB Cellular infrastructure Point-to-point wireless

The AD9789 is a flexible QAM encoder/interpolator/upconverter combined with a high performance, 2400 MSPS, 14-bit RF digital-to-analog converter (DAC). The flexible digital interface can accept up to four channels of complex data. The QAM encoder supports constellation sizes of 16, 32, 64, 128, and 256 with SRRC filter coefficients for all standards.

The on-chip rate converter supports a wide range of baud rates with a fixed DAC clock. The digital upconverter can place the channels from 0 to 0.5 × fDAC. This permits four contiguous channels to be synthesized and placed anywhere from dc to fDAC/2.

The AD9789 includes a serial peripheral interface (SPI) for device configuration and status register readback. The flexible digital interface can be configured for data bus widths of 4, 8, 16, and 32 bits. It can accept real or complex data.

The AD9789 operates from 1.5 V, 1.8 V, and 3.3 V supplies for a total power consumption of 1.6 W. It is supplied in a 164-ball chip scale package ball grid array for lower thermal impedance and reduced package parasitics. No special power sequencing is required. The clock receiver powers up muted to prevent start-up noise.

Product Highlights

• Highly integrated and configurable QAM mappers, interpolators, and upconverters for direct synthesis of 1 to 4 DOCSIS or DVB compatible channels in a block.
• Low noise and intermodulation distortion (IMD) performance enable high quality synthesis of signals up to 1 GHz.
• Flexible data interface supports LVDS for outstanding SFDR or CMOS input data for less demanding applications.
• Interface is configurable from 4-bit nibbles to 32-bit words and can run at up to 150 MHz CMOS or 150 MHz LVDS DDR.
• Manufactured on a CMOS process, the AD9789 uses a proprietary switching technique that enhances dynamic performance.

Applications

• Broadband communications systems
• CMTS/DVB
• Cellular infrastructure
• Point-to-point wireless

Data Sheets

Order Information

Evaluation Boards

Reference Materials

• Solutions Bulletins & Brochures：Digital to Analog Converters ICs Solutions Bulletin
• Solutions Bulletins & Brochures：Digital-to-Analog Converter ICs Solutions Bulletin, Volume 10, Issue 1