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ADP5033 Dual 3 MHz, 800 mA Buck Regulators with Two 300 mA LDOs

The ADP5033 combines two high performance buck regulators and two low dropout regulators (LDO) in a tiny, 16-ball, 2 mm × 2 mm WLCSP to meet demanding performance and board space requirements.

The high switching frequency of the buck regulators enables tiny multilayer external components and minimizes the board space. When the MODE pin is set high, the buck regulators operate in forced PWM mode. When the MODE pin is set low, the buck regulators operate in forced power save mode (PSM). When the load is around the nominal value and the load current falls below a predefined threshold, the regulator operates in PSM, improving the light load efficiency.

The two bucks operate out of phase to reduce the input capacitor requirement and noise.

The low quiescent current, low dropout voltage, and wide input voltage range of the ADP5033 LDO extend the battery life of portable devices. The ADP5033 LDOs maintain power supply rejection greater than 60 dB for frequencies as high as 10 kHz while operating with a low headroom voltage.

The regulators in the ADP5033 are activated by the ENA and ENB pins. The specific channels controlled by ENA and ENB are set by factory programming. A high voltage level applied to the enable pins activates the regulators. The default output voltages are factory programmable and can be set to a wide range of options.

Applications

• Power for processors, ASICS, FPGAs, and RF chipsets
• Portable instrumentation and medical devices
• Space constrained devices

Data Sheets

User Guides

Order Information

Evaluation Boards

Reference Materials

• Solutions Bulletins & Brochures：Integrated, High Power Solutions for Xilinx FPGAs
• Solutions Bulletins & Brochures：Integrated Power Solutions for Altera FPGAs