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XRT75L00:Single-Chip Line Interface Unit (LIU) With Jitter Attenuator (JA) for DS3/E3/STS-1 Environments

With an established, and industry proven series of physical layer, access and metro products, Exar extends its capabilities by releasing the XRT75L00, a single-channel DS3/E3/STS-1 Line Interface Unit (LIU) with an independent receiver, transmitter and jitter attenuator. Using an innovative combination of analog and digital signal processing technologies, this new approach will be embedded in Exar's physical interface and data aggregation devices.

Jitter is caused by many factors: cross-talk noise, imperfect timing recovery circuitry, or line interface/signal distortion. Typical corporate Wide Area Network (WAN) environments contain many pieces of equipment, where at each connection point (node) jitter can increase, and as a result new errors can be introduced into data transmitted throughout the system.

The XRT75L00 is the next generation solution for the design challenges presented by jitter. Previously, Exar launched the XRT71D00, the industry's first standards compliant jitter attenuator for DS3/E3 applications. It was soon followed by the industry's first multi-channel jitter attenuators (XRT71D03 and XRT71D04).

Product Highlights

The XRT75L00D has an independent receiver, transmitter and jitter attenuator in a single 52-pin TQFP package. It supports E3 (34.368.Mbps), DS3 (44.736Mbps) and STS-1 (51.84 Mbps) operations, has a differential receiver which provides a high noise interference margins -- capable of receiving data from cables of over 1,000 feet, or up to 12dB of cable attenuation. The device has an onboard Pseudo Random Binary Sequence (PRBS) generator and detector that can insert and detect single bit errors. This function is often used for diagnostic purposes. The XRT75L00D provides both serial microprocessor interface as well as hardware mode for additional programming and control. It also supports local, remote and digital loop-backs.

Standard's Compliance

The receiver, transmitter, and jitter attenuator all meet Bellcore GR-499 CORE requirements. Also, the transmitter meets the GR-253 CORE and ANSI T1.102 specifications and it includes a duty cycle correction PLL. The device meets jitter and wander specifications described in the T1.105.03b, and ETSI TBR-24, and is compliant with jitter transfer templates outlined in ITU G.751, G.752 and G.755.

技术特性
  • On-Chip Clock and Data Recovery Circuit for High-Input Jitter Tolerance
  • On-Chip B3ZS/HDB3 Encoder/Decoder Can be Disabled or Enabled
  • Tri-state Transmit Output Capability for Redundancy Applications
  • Transmitter Can be Turned On or Off
  • Jitter Attenuator Can be Selected in Receive or Transmit Paths
  • Selectable FIFO Size of 16 or 32 Bits
  • Five Wire Serial Microprocessor for Control and Configuration
  • Supports Optional Internal Transmit Driver Monitoring
  • Pb-Free, RoHS Compliant Versions Offered
数据手册S
应用指南
电路图
Product Change Notification
产品应用
  • E3/DS3 Access Equipment
  • STS-1-SPE to DS# Mapper
  • DSLAMs
  • Digital Cross Connect Systems
  • CSU/DSC Equipment
  • Routers
  • Fiber Optic Terminals
规格参数
频道数量1
数据传输速率(s)DS3, E3, STS-1
Clk RecYes
短途/长途n/a
温度.范围Ind.
Op Pwr Sup/ Max Cur3V ±5%
封装TQFP-52
Recommended
订购型号
器件型号封装编码最低温度最高温度状态
XRT75L00IVTQFP52-4085EOL
XRT75L00IV-FTQFP52-4085Active
XRT75VL00IVTREOL
十二月 2013 XR68M752
三月 2013 XRT91L31
十月 2013 XR19L212