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74LVX244: Low Voltage Octal Buffer/Line Driver with 3-STATE Outputs
The LVX244 is an octal non-inverting buffer and line driver designed to be employed as a memory address driver, clock driver and bus oriented transmitter or receiver which provides improved PC board density. The inputs tolerate up to 7V allowing interface of 5V systems to 3V systems.
| 74LVX244 Datasheet |
Features
- Input voltage translation from 5V to 3V
- Ideal for low power/low noise 3.3V applications
- Guaranteed simultaneous switching noise level and dynamic threshold performance
| Product | Product & Eco Status | Unit Price/1K Order | Packing Method Convention | Package Marking Convention* |
|---|---|---|---|---|
| 74LVX244MTC | Full Production Green as of Aug 2011 China RoHS | $0.2 | TSSOP 20L
-
1.2 x 4.4 x 6.5mm,
RAIL
| Line 1$Y (Fairchild logo) &Z (Plant Code) &2 (2-Digit Date Code) &K
Line 2LVX244 |
| 74LVX244M | Full Production Green as of Dec 2015 China RoHS | $0.22 | SO 20L WB
-
2.337 x 7.468 x 15.342mm,
RAIL
| Line 1$Y (Fairchild logo) &Z (Plant Code) &2 (2-Digit Date Code) &K
Line 2LVX244 |
| 74LVX244MTCX | Full Production Green as of Aug 2011 China RoHS | $0.1855 | TSSOP 20L
-
1.2 x 4.4 x 6.5mm,
TAPE REEL
| Line 1$Y (Fairchild logo) &Z (Plant Code) &2 (2-Digit Date Code) &K
Line 2LVX244 |
| 74LVX244SJ | Obsolete as of 10-Jun-2013 ROHS Compliant as of 27-Feb-2006 Replacement Part: 74LVX244SJX China RoHS | N/A | SOP 20L
-
1.8 x 5.3 x 12.6mm,
RAIL
| Line 1$Y (Fairchild logo) &Z (Plant Code) &2 (2-Digit Date Code) &K
Line 2LVX244 |
| 74LVX244MX | Full Production Green as of Dec 2015 China RoHS | $0.3232 | SO 20L WB
-
2.337 x 7.468 x 15.342mm,
TAPE REEL
| Line 1$Y (Fairchild logo) &Z (Plant Code) &2 (2-Digit Date Code) &K
Line 2LVX244 |
| 74LVX244SJX | Full Production ROHS Compliant as of 27-Feb-2006 China RoHS | $0.4638 | SOP 20L
-
1.8 x 5.3 x 12.6mm,
TAPE REEL
| Line 1$Y (Fairchild logo) &Z (Plant Code) &2 (2-Digit Date Code) &K
Line 2LVX244 |
Application Notes
- TSSOP 20L Drawing Last Update: Jan 2015
- MTC20 TSSOP20 Leads, Packing Drawing Last Update: Jan 2016
- SO 20L WB Drawing Last Update: Feb 2013
- M20B SOW20, Packing Drawing Last Update: Jan 2016
- SOIC Tape And Reel Packing Drawing Last Update: Jun 2016
- SOP 20L Drawing Last Update: Nov 2015
- M20D SOP EIAJ 20L, Packing Drawing Last Update: Jan 2016
- SOIC TUBE Packing Drawing Last Update: Dec 2016
- Using Fairchilds LVX Low Voltage Dual Supply CMOS Translating Transceivers Last Update : 28-Jun-2014
