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74LVX373: Low Voltage Octal Transparent Latch with 3-STATE Outputs
The LVX373 consists of eight latches with 3-STATE outputs for bus organized system applications. The latches appear transparent to the data when Latch Enable (LE) is HIGH. When LE is LOW, the data satisfying the input timing requirements is latched. Data appears on the bus when the Output Enable (OE#) is LOW. When OE# is HIGH, the bus output is in the high impedance state. The inputs tolerate up to 7V allowing interface of 5V systems to 3V systems.
| 74LVX373 Datasheet |
Features
- Input voltage translation from 5V to 3V
- Ideal for low power/low noise 3.3V applications
- Guaranteed simultaneous switching noise level and dynamic threshold performance
| Product | Product & Eco Status | Unit Price/1K Order | Packing Method Convention | Package Marking Convention* |
|---|---|---|---|---|
| 74LVX373MTC | Obsolete as of 10-Jun-2013 Green as of Aug 2011 Replacement Part: 74LVX373MTCX China RoHS | N/A | TSSOP 20L
-
1.2 x 4.4 x 6.5mm,
RAIL
| Line 1$Y (Fairchild logo) &Z (Plant Code) &2 (2-Digit Date Code) &K
Line 2LVX373 |
| 74LVX373M | Full Production Green as of Dec 2015 China RoHS | $0.22 | SO 20L WB
-
2.337 x 7.468 x 15.342mm,
RAIL
| Line 1$Y (Fairchild logo) &Z (Plant Code) &2 (2-Digit Date Code) &K
Line 2LVX373 |
| 74LVX373MTCX | Full Production Green as of Aug 2011 China RoHS | $0.2185 | TSSOP 20L
-
1.2 x 4.4 x 6.5mm,
TAPE REEL
| Line 1$Y (Fairchild logo) &Z (Plant Code) &2 (2-Digit Date Code) &K
Line 2LVX373 |
| 74LVX373SJ | Obsolete as of 23-Sep-2010 ROHS Compliant as of 27-Feb-2006 Replacement Part: None China RoHS | N/A | SOP 20L
-
1.8 x 5.3 x 12.6mm,
RAIL
| Line 1$Y (Fairchild logo) &Z (Plant Code) &2 (2-Digit Date Code) &K
|
| 74LVX373MX | Obsolete as of 10-Jun-2013 ROHS Compliant as of 27-Feb-2006 Replacement Part: 74LVX373MTCX China RoHS | N/A | SO 20L WB
-
2.337 x 7.468 x 15.342mm,
TAPE REEL
| Line 1$Y (Fairchild logo) &Z (Plant Code) &2 (2-Digit Date Code) &K
Line 2LVX373 |
Application Notes
- TSSOP 20L Drawing Last Update: Jan 2015
- MTC20 TSSOP20 Leads, Packing Drawing Last Update: Jan 2016
- SO 20L WB Drawing Last Update: Feb 2013
- M20B SOW20, Packing Drawing Last Update: Jan 2016
- SOIC Tape And Reel Packing Drawing Last Update: Jun 2016
- SOP 20L Drawing Last Update: Nov 2015
- M20D SOP EIAJ 20L, Packing Drawing Last Update: Jan 2016
- SOIC TUBE Packing Drawing Last Update: Dec 2016
- Using Fairchilds LVX Low Voltage Dual Supply CMOS Translating Transceivers Last Update : 28-Jun-2014
