FIN1002: 3.3V LVDS 1-Bit High Speed Differential Receiver

This single receiver is designed for high speed interconnects utilizing Low Voltage Differential Signaling (LVDS) technology. The receiver translates LVDS levels, with a typical differential input threshold of 100 mV, to LVTTL signal levels. LVDS provides low EMI at ultra low power dissipation even at high frequencies. This device is ideal for high speed transfer of clock or data. The FIN1002 can be paired with its companion driver, the FIN1001, or with any other LVDS driver.

FIN1002 Datasheet

Features

Greater than 400Mbs data rate
3.3V power supply operation
0.4ns maximum pulse skew
2.5ns maximum propagation delay
Bus pin ESD (HBM) protection exceeds 10kV
Power-Off over voltage tolerant input and output
Fail safe protection for open-circuit and non-driven, shorted or terminated conditions
High impedance output at V_CC < 1.5V
Meets or exceeds the TIA/EIA-644 LVDS standard
5-Lead SOT23 package saves space

**Ordering Code**
Product	Product & Eco Status	Unit Price/1K Order	Packing Method Convention	Package Marking Convention*
FIN1002M5X	Full Production Green as of Jun 2012 China RoHS	$0.286	SOT-23 5L - 1.3 x 3.0 x 1.7mm, TAPE REEL SOT-23 5L Drawing Last Update: Oct 2015 SOT Tape and Reel Packing Drawing Last Update: Oct 2016	Line 1&E (Space) &E (Space) &Y (Binary Calendar Year Coding) Line 2&O (Plant Code) FN02&C (Die Run) Line 3&. (Pin One) &O (Plant Code) &E (Space) &V (Eight Week Binary Datecoding)
FIN1002M5	Obsolete as of 21-Sep-2011 ROHS Compliant as of 27-Feb-2006 Replacement Part: FIN1002M5X China RoHS	N/A	SOT-23 5L - 1.3 x 3.0 x 1.7mm, TAPE REEL SOT-23 5L Drawing Last Update: Oct 2015 SOT Tape and Reel Packing Drawing Last Update: Oct 2016	Line 1&E (Space) &E (Space) &Y (Binary Calendar Year Coding)