FIN1018: 3.3V LVDS 1-Bit High Speed Differential Receiver

This single receiver is designed for high speed interconnects utilizing Low Voltage Differential Signaling (LVDS) technology. The receiver translates LVDS levels, with a typical differential input threshold of 100 mV, to LVTTL signal levels. LVDS provides low EMI at ultra low power dissipation even at high frequencies. This device is ideal for high speed transfer of clock or data.     The FIN1018 can be paired with its companion driver, the FIN1017, or with any other LVDS driver.

Features

• Greater than 400Mbs data rate
• 3.3V power supply operation
• 0.4ns maximum pulse skew
• 2.5ns maximum propagation delay
• Low power dissipation
• Power-Off protection
• Fail safe protection for open-circuit, shorted and terminated conditions
• Meets or exceeds the TIA/EIA-644 LVDS standard
• Flow-through pinout simplifies PCB layout
• 8-Lead SOIC and US-8 packages save space

Application Notes