Features

• High Speed Serial Interface (JESD204)
• Sample Rate: 105Msps
• 77.7dBFS Noise Floor
• 100dB SFDR
• SFDR >82dB at 250MHz (1.5VP-P Input Range)
• PGA Front End (2.25VP-P or 1.5VP-P Input Range)
• 700MHz Full Power Bandwidth S/H
• Optional Internal Dither
• Single 3.3V Supply
• Power Dissipation: 1300mW
• Clock Duty Cycle Stabilizer
• Pin Compatible Family 105Msps: LTC2274 80Msps: LTC2273 65Msps: LTC2272
• 40-Pin 6mm × 6mm QFN Package

Typical Application

Applications

• Telecommunications
• Receivers
• Cellular Base Stations
• Spectrum Analysis
• Imaging Systems
• ATE

Packaging

Datasheet

• LTC2274 - 16-Bit, 105Msps Serial Output ADC

Design Note

• DN468 - Maximize the Performance of 16-Bit, 105Msps ADC with Careful IF SIgnal Chain Design

Reliability Data

• R478 - Reliability Data

Product Selector Card

• High Speed Amplifiers/ADC Drivers
• Low Power, 16-Bit Dual/Single ADCs

LT Journal

• December 2009 - Maximize the Performance of 16-Bit, 105Msps ADC with Careful IF Signal Chain Design
• September 2008 - Serial Interface for High Speed Data Converters Simplifies Layout over Traditional Parallel Devices

Press Release

• 16-bit, 105Msps Serial Output ADC Conserves FPGA I/O Pins

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