74ALVCH16821DL: 20-bit bus-interface D-type flip-flop' positive-edge trigger (3-State)

The 74ALVCH16821 has two 10-bit, edge triggered registers, with each register coupled to a 3-State output buffer. The two sections of each register are controlled independently by the clock (nCP) and Output Enable (nOE) control gates.

Each register is fully edge triggered. The state of each D input, one set-up time before the Low-to-High clock transition, is transferred to the corresponding flip-flop's Q output.

When nOE is LOW, the data in the register appears at the outputs. When nOE is HIGH, the outputs are in high impedance OFF state. Operation of the nOE input does not affect the state of the flip-flops.

The 74ALVCH16821 has active bus hold circuitry which is provided to hold unused or floating data inputs at a valid logic level. This feature eliminates the need for external pull-up or pull-down resistors.

74ALVCH16821DL: Product Block Diagram

Outline 3d SOT371-1

Data Sheets (1)

Name/Description	Modified Date
20-bit bus-interface D-type flip-flop' positive-edge trigger (3-state) (REV 2.0) PDF (95.0 kB) 74ALVCH16821 [English]	14 Mar 2014

Application Notes (5)

Name/Description	Modified Date
Sorting through the low voltage logic maze (REV 1.0) PDF (72.0 kB) AN10156 [English]	13 Mar 2013
Package lead inductance considerations in high-speed applications (REV 1.0) PDF (43.0 kB) AN212 [English]	13 Mar 2013
Ground and VCC Bounce of High-Speed Integrated Circuits (REV 1.0) PDF (25.0 kB) AN223 [English]	13 Mar 2013
Live Insertion Aspects of Philips Logic Families (REV 1.0) PDF (73.0 kB) AN252 [English]	13 Mar 2013
Interfacing 3 Volt and 5 Volt Applications (REV 1.0) PDF (63.0 kB) AN240 [English]	15 Sep 1995

Brochures (3)

Name/Description	Modified Date
Low voltage CMOS family - LVC (REV 1.0) PDF (2.6 MB) 75017668 [English]	10 Jul 2015
電圧レベルシフタ (REV 1.1) PDF (3.1 MB) 75017511_JP [English]	16 Feb 2015
Voltage translation: How to manage mixed-voltage designs with NXP® level translators (REV 1.0) PDF (2.6 MB) 75017511 [English]	20 May 2014

Selector Guides (2)

Name/Description	Modified Date
ロジック製品セレクションガイド... (REV 1.0) PDF (38.3 MB) LOGIC_SELECTION_GUIDE_2015_JP [English]	19 Nov 2015
Logic selection guide 2016 (REV 1.1) PDF (15.3 MB) 75017285 [English]	08 Jan 2015

Package Information (1)

Name/Description	Modified Date
plastic shrink small outline package; 56 leads; body width 7.5 mm (REV 1.0) PDF (530.0 kB) SOT371-1 [English]	08 Feb 2016

Supporting Information (2)

Name/Description	Modified Date
Footprint for reflow soldering (REV 1.0) PDF (16.0 kB) SSOP-TSSOP-VSO-REFLOW [English]	08 Oct 2009
Footprint for wave soldering (REV 1.0) PDF (16.0 kB) SSOP-TSSOP-VSO-WAVE [English]	08 Oct 2009

IBIS Model

alvch16821 IBIS model (REV 1.0) ibs ALVCH16821 4/7/2013

Ordering Information

Product	Status	Family	V_CC (V)	Function	Logic switching levels	Description	Output drive capability (mA)	Package version	t_pd (ns)	f_max (MHz)	Power dissipation considerations	T_amb (Cel)	R_th(j-a) (K/W)	Ψ_th(j-top) (K/W)	R_th(j-c) (K/W)	Package name	No of pins
74ALVCH16821DL	Active	ALVC	2.3 - 3.6	D-type flip-flops	TTL	positive-edge trigger (3-state)	+/- 24	SOT371-1	2.5	350	low	-40~85	84	24.0		SSOP56	56

Package Information

Product ID	Outline Version	Reflow/Wave Soldering	Packing	Product Status	Part NumberOrdering code(12NC)	Marking	Chemical Content	LeadFree Conversion Date	EFR	IFR(FIT)	MTBF(hour)	MSL	MSL LF
74ALVCH16821DL	SOT371-1	SSOP-TSSOP-VSO-REFLOW SSOP-TSSOP-VSO-WAVE SSOP-TSSOP-VSO-REFLOW SSOP-TSSOP-VSO-WAVE	Tube in Drypack	Active	74ALVCH16821DL,512 (9352 590 00512)	ALVCH16821	74ALVCH16821DL	week 13, 2005	123.8	3.87	2.58E8	1	2
			Reel 13" Q1/T1 in Drypack	Active	74ALVCH16821DL,518 (9352 590 00518)	ALVCH16821	74ALVCH16821DL	week 13, 2005	123.8	3.87	2.58E8	1	2
			Reel 13" Q1/T1	Withdrawn	74ALVCH16821DL,118 (9352 590 00118)	ALVCH16821	74ALVCH16821DL	Always Pb-free	123.8	3.87	2.58E8	1	1