74AUP1G04GV: Low-power inverter
The 74AUP1G04 provides the single inverting buffer.
Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire VCC range from 0.8 V to 3.6 V.
This device ensures a very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V.
This device is fully specified for partial Power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down.
74AUP1G04GV: Product Block Diagram
Outline 3d SOT753
Data Sheets (1)
| Name/Description | Modified Date |
|---|---|
| Low-power inverter (REV 7.0) PDF (416.0 kB) 74AUP1G04 [English] | 27 Jun 2012 |
Application Notes (2)
| Name/Description | Modified Date |
|---|---|
| Sorting through the low voltage logic maze (REV 1.0) PDF (72.0 kB) AN10156 [English] | 13 Mar 2013 |
| Pin FMEA for AUP family (REV 1.0) PDF (53.0 kB) AN11052 [English] | 06 May 2011 |
Brochures (3)
| Name/Description | Modified Date |
|---|---|
| 電圧レベルシフタ (REV 1.1) PDF (3.1 MB) 75017511_JP [English] | 16 Feb 2015 |
| NXP® ultra-low-power CMOS logic 74AUP1G/2G/3Gxxx: Advanced, ultra-low-power CMOS logic (REV 1.0) PDF (1.4 MB) 75017458 [English] | 13 Oct 2014 |
| Voltage translation: How to manage mixed-voltage designs with NXP® level translators (REV 1.0) PDF (2.6 MB) 75017511 [English] | 20 May 2014 |
Selector Guides (2)
| Name/Description | Modified Date |
|---|---|
| ロジック製品セレクションガイド... (REV 1.0) PDF (38.3 MB) LOGIC_SELECTION_GUIDE_2015_JP [English] | 19 Nov 2015 |
| Logic selection guide 2016 (REV 1.1) PDF (15.3 MB) 75017285 [English] | 08 Jan 2015 |
Package Information (1)
| Name/Description | Modified Date |
|---|---|
| plastic surface-mounted package; 5 leads (REV 1.0) PDF (243.0 kB) SOT753 [English] | 08 Feb 2016 |
Packing (1)
| Name/Description | Modified Date |
|---|---|
| Tape reel SMD; reversed product orientation 12NC ending 125 (REV 1.0) PDF (186.0 kB) SOT753_125 [English] | 29 Nov 2012 |
Supporting Information (1)
| Name/Description | Modified Date |
|---|---|
| MAR_SOT753 Topmark (REV 1.0) PDF (89.0 kB) MAR_SOT753 [English] | 03 Jun 2013 |
IBIS Model
- 74AUP1G04 IBIS model (REV 1.0) ibs AUP1G04 12/15/2014
Ordering Information
| Product | Status | Family | VCC (V) | Function | Logic switching levels | Description | Output drive capability (mA) | Package version | fmax (MHz) | No of bits | tpd (ns) | Power dissipation considerations | Tamb (Cel) | Rth(j-a) (K/W) | Ψth(j-top) (K/W) | Rth(j-c) (K/W) | Package name | No of pins |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 74AUP1G04GV | Active | AUP | 1.1 - 3.6 | Buffers/inverters/drivers | CMOS | single inverter | +/- 1.9 | SOT753 | 70 | 1 | 4 | ultra low | -40~125 | 268 | 62.1 | 167 | TSOP5 | 5 |
Package Information
| Product ID | Package Description | Outline Version | Reflow/Wave Soldering | Packing | Product Status | Part NumberOrdering code(12NC) | Marking | Chemical Content | RoHS / Pb Free / RHF | LeadFree Conversion Date | MSL | MSL LF |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 74AUP1G04GV | | SOT753 | Reel 7" Q3/T4, Reverse | Active | 74AUP1G04GV,125 (9352 906 76125) | p04 | 74AUP1G04GV |    | Always Pb-free | 1 | 1 |
- Low-power inverter 74AUP1G04GW
- Sorting through the low voltage logic maze 74LVC_H_245A_Q100
- Pin FMEA for AUP family 74AUP1T34GW-Q100
- 電圧レベルシフタ 74AVC16245DGG-Q100
- NXP® ultra-low-power CMOS logic 74AUP1G/2G/3Gxxx: Advanced, ultra-low-power CMOS logic 74AUP1G86GW-Q100
- Voltage translation: How to manage mixed-voltage designs with NXP® level translators 74AVC16245DGG-Q100
- ロジック製品セレクションガイド... 74LVC_H_245A_Q100
- Logic selection guide 2016 74LVC_H_245A_Q100
- MAR_SOT753 Topmark 74LVC1G17_Q100
- 74AUP1G04 IBIS model 74AUP1G04GW
- plastic surface-mounted package; 5 leads 74LVC1G17_Q100
- Tape reel SMD; reversed product orientation 12NC ending 125 74LVC1G17_Q100
- 74AVCM162836DGG
- BAP70Q
