The 74AUP1G126 provides a single non-inverting buffer/line driver with 3-state output. The 3-state output is controlled by the output enable input (OE). A LOW level at pin OE causes the output to assume a high-impedance OFF-state. This device has the input-disable feature, which allows floating input signals. The inputs are disabled when the output enable input OE is LOW.
Schmitt-trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire VCC range from 0.8 V to 3.6 V. This device ensures a very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V.
This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing a damaging backflow current through the device when it is powered down.
Name/Description | Modified Date |
---|---|
Low-power buffer/line-driver; 3-state (REV 6.0) PDF (207.0 kB) 74AUP1G126 [English] | 02 Oct 2015 |
Name/Description | Modified Date |
---|---|
Sorting through the low voltage logic maze (REV 1.0) PDF (72.0 kB) AN10156 [English] | 13 Mar 2013 |
Pin FMEA for AUP family (REV 1.0) PDF (53.0 kB) AN11052 [English] | 06 May 2011 |
Name/Description | Modified Date |
---|---|
電圧レベルシフタ (REV 1.1) PDF (3.1 MB) 75017511_JP [English] | 16 Feb 2015 |
NXP® ultra-low-power CMOS logic 74AUP1G/2G/3Gxxx: Advanced, ultra-low-power CMOS logic (REV 1.0) PDF (1.4 MB) 75017458 [English] | 13 Oct 2014 |
Voltage translation: How to manage mixed-voltage designs with NXP® level translators (REV 1.0) PDF (2.6 MB) 75017511 [English] | 20 May 2014 |
Name/Description | Modified Date |
---|---|
ロジック製品セレクションガイド... (REV 1.0) PDF (38.3 MB) LOGIC_SELECTION_GUIDE_2015_JP [English] | 19 Nov 2015 |
Logic selection guide 2016 (REV 1.1) PDF (15.3 MB) 75017285 [English] | 08 Jan 2015 |
Name/Description | Modified Date |
---|---|
extremely thin small outline package; no leads; 6 terminals (REV 1.0) PDF (176.0 kB) SOT1115 [English] | 08 Feb 2016 |
Name/Description | Modified Date |
---|---|
Reversed product orientation 12NC ending 132 (REV 2.0) PDF (92.0 kB) SOT1115_132 [English] | 04 Apr 2013 |
Name/Description | Modified Date |
---|---|
MAR_SOT1115 Topmark (REV 1.0) PDF (47.0 kB) MAR_SOT1115 [English] | 03 Jun 2013 |
Product | Status | Family | Function | VCC (V) | Description | Logic switching levels | Output drive capability (mA) | Package version | fmax (MHz) | No of bits | Power dissipation considerations | tpd (ns) | Tamb (Cel) | Rth(j-a) (K/W) | Ψth(j-top) (K/W) | Rth(j-c) (K/W) | Package name | No of pins |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
74AUP1G126GN | Active | AUP | Buffers/inverters/drivers | 1.1 - 3.6 | single buffer/line driver (3-state) | CMOS | +/- 1.9 | SOT1115 | 70 | 1 | ultra low | 4.3 | -40~125 | 334 | 22.6 | 207 | XSON6 | 6 |
Product ID | Package Description | Outline Version | Reflow/Wave Soldering | Packing | Product Status | Part NumberOrdering code(12NC) | Marking | Chemical Content | RoHS / Pb Free / RHF | LeadFree Conversion Date | MSL | MSL LF |
---|---|---|---|---|---|---|---|---|---|---|---|---|
74AUP1G126GN | SOT1115 | Reel 7" Q1/T1, Q3/T4 | Active | 74AUP1G126GN,132 (9352 917 23132) | pN | 74AUP1G126GN | Always Pb-free | 1 | 1 |