74AUP2G79DC-Q100: Low-power dual D-type flip-flop; positive-edge trigger

The 74AUP2G79-Q100 provides the dual positive-edge triggered D‑type flip‑flop. Information on the data input (nD) is transferred to the nQ output on the LOW‑to‑HIGH transition of the clock pulse (nCP). The nD input must be stable one set-up time prior to the LOW‑to‑HIGH clock transition for predictable operation.

Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire VCC range from 0.8 V to 3.6 V.

This device ensures a very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V.

This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing a damaging backflow current through the device when it is powered down.

This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications.

74AUP2G79DC-Q100: Product Block Diagram

Outline 3d SOT765-1

Data Sheets (1)

Name/Description	Modified Date
Low-power dual D-type flip-flop; positive-edge trigger (REV 1.0) PDF (121.0 kB) 74AUP2G79_Q100	11 Jun 2013

Application Notes (1)

Name/Description	Modified Date
Pin FMEA for AUP family (REV 1.0) PDF (53.0 kB) AN11052	06 May 2011

Brochures (3)

Name/Description	Modified Date
電圧レベルシフタ (REV 1.1) PDF (3.1 MB) 75017511_JP	16 Feb 2015
NXP® ultra-low-power CMOS logic 74AUP1G/2G/3Gxxx: Advanced, ultra-low-power CMOS logic (REV 1.0) PDF (1.4 MB) 75017458	13 Oct 2014
Voltage translation: How to manage mixed-voltage designs with NXP® level translators (REV 1.0) PDF (2.6 MB) 75017511	20 May 2014

Selector Guides (2)

Name/Description	Modified Date
ロジック製品セレクションガイド... (REV 1.0) PDF (38.3 MB) LOGIC_SELECTION_GUIDE_2015_JP	19 Nov 2015
Logic selection guide 2016 (REV 1.1) PDF (15.3 MB) 75017285	08 Jan 2015

Package Information (1)

Name/Description	Modified Date
plastic very thin shrink small outline package; 8 leads; body width 2.3 mm (REV 1.1) PDF (245.0 kB) SOT765-1	05 Jul 2016

Packing (1)

Name/Description	Modified Date
VSSOP8; Reel pack, reverse; SMD, 7" Q3/T4 Standard product orientation Orderable part number ending ,125 or... (REV 5.0) PDF (210.0 kB) SOT765-1_125	03 May 2013

Ordering Information

Product	Status	Family	V_CC (V)	Description	Logic switching levels	Output drive capability (mA)	t_pd (ns)	f_max (MHz)	Power dissipation considerations	T_amb (Cel)	R_th(j-a) (K/W)	Ψ_th(j-top) (K/W)	R_th(j-c) (K/W)	Package name	No of pins	Package version
74AUP2G79DC-Q100	Active	AUP	1.1 - 3.6	dual D-type flip-flop	CMOS	+/- 1.9	8.5	400	ultra low	-40~125	203	34.1	113	VSSOP8	8	SOT765-1

Package Information

Product ID	Package Description	Outline Version	Reflow/Wave Soldering	Packing	Product Status	Part NumberOrdering code(12NC)	Marking	Chemical Content	RoHS / Pb Free / RHF	LeadFree Conversion Date	MSL	MSL LF
74AUP2G79DC-Q100		SOT765-1		Reel 7" Q3/T4, Reverse	Active	74AUP2G79DC-Q100H (9353 016 64125)	p79	74AUP2G79DC-Q100		Always Pb-free	1	1