74AUP2G79GD: Low-power dual D-type flip-flop; positive-edge trigger
The 74AUP2G79 provides the dual positive-edge triggered D-type flip-flop. Information on the data input (nD) is transferred to the nQ output on the LOW-to-HIGH transition of the clock pulse (nCP). The nD input must be stable one set-up time prior to the LOW-to-HIGH clock transition for predictable operation.
Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire VCC range from 0.8 V to 3.6 V.
This device ensures a very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V.
This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing a damaging backflow current through the device when it is powered down.
74AUP2G79GD: Product Block Diagram
Outline 3d SOT996-2
Data Sheets (1)
| Name/Description | Modified Date |
|---|---|
| Low-power dual D-type flip-flop; positive-edge trigger (REV 8.0) PDF (291.0 kB) 74AUP2G79 [English] | 24 Jan 2013 |
Application Notes (4)
| Name/Description | Modified Date |
|---|---|
| Sorting through the low voltage logic maze (REV 1.0) PDF (72.0 kB) AN10156 [English] | 13 Mar 2013 |
| Pin FMEA for AUP family (REV 1.0) PDF (53.0 kB) AN11052 [English] | 06 May 2011 |
| MicroPak soldering information (REV 2.0) PDF (245.0 kB) AN10343 [English] | 30 Dec 2010 |
| PicoGate Logic footprints (REV 1.0) PDF (87.0 kB) AN10161 [English] | 30 Oct 2002 |
Brochures (3)
| Name/Description | Modified Date |
|---|---|
| 電圧レベルシフタ (REV 1.1) PDF (3.1 MB) 75017511_JP [English] | 16 Feb 2015 |
| NXP® ultra-low-power CMOS logic 74AUP1G/2G/3Gxxx: Advanced, ultra-low-power CMOS logic (REV 1.0) PDF (1.4 MB) 75017458 [English] | 13 Oct 2014 |
| Voltage translation: How to manage mixed-voltage designs with NXP® level translators (REV 1.0) PDF (2.6 MB) 75017511 [English] | 20 May 2014 |
Selector Guides (2)
| Name/Description | Modified Date |
|---|---|
| ロジック製品セレクションガイド... (REV 1.0) PDF (38.3 MB) LOGIC_SELECTION_GUIDE_2015_JP [English] | 19 Nov 2015 |
| Logic selection guide 2016 (REV 1.1) PDF (15.3 MB) 75017285 [English] | 08 Jan 2015 |
Package Information (1)
| Name/Description | Modified Date |
|---|---|
| plastic extremely thin small outline package; no leads; 8 terminals; body 3 x 2 x 0.5 mm (REV 1.0) PDF (190.0 kB) SOT996-2 [English] | 08 Feb 2016 |
Packing (1)
| Name/Description | Modified Date |
|---|---|
| XSON8(U); Reel pack, Reverse; SMD, 7" Q3/T4 Standard product orientation Orderable part number ending ,125 or... (REV 5.0) PDF (200.0 kB) SOT996-2_125 [English] | 02 May 2013 |
IBIS Model
- aup2g79 IBIS model (REV 1.1) ibs AUP2G79 4/8/2013
Ordering Information
| Product | Status | Family | VCC (V) | Function | Logic switching levels | Description | Package version | Output drive capability (mA) | tpd (ns) | fmax (MHz) | Power dissipation considerations | Tamb (Cel) | Rth(j-a) (K/W) | Ψth(j-top) (K/W) | Rth(j-c) (K/W) | Package name | No of pins |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 74AUP2G79GD | Active | AUP | 1.1 - 3.6 | D-type flip-flops | CMOS | positive-edge trigger | SOT996-2 | +/- 1.9 | 8.5 | 400 | ultra low | -40~125 | 610 | 80.8 | 271 | XSON8 | 8 |
Package Information
| Product ID | Package Description | Outline Version | Reflow/Wave Soldering | Packing | Product Status | Part NumberOrdering code(12NC) | Marking | Chemical Content | RoHS / Pb Free / RHF | LeadFree Conversion Date | EFR | IFR(FIT) | MTBF(hour) | MSL | MSL LF |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 74AUP2G79GD | | SOT996-2 | Reel 7" Q3/T4, Reverse | Active | 74AUP2G79GD,125 (9352 888 73125) | p79 | 74AUP2G79GD |    | Always Pb-free | 0.0 | 3.29 | 3.04E8 | 1 | 1 |
- Sorting through the low voltage logic maze 74LVC_H_245A_Q100
- Pin FMEA for AUP family 74AUP1T34GW-Q100
- MicroPak soldering information NTS0102_Q100
- PicoGate Logic footprints NX3L4684
- 電圧レベルシフタ 74AVC16245DGG-Q100
- NXP® ultra-low-power CMOS logic 74AUP1G/2G/3Gxxx: Advanced, ultra-low-power CMOS logic 74AUP1G86GW-Q100
- Voltage translation: How to manage mixed-voltage designs with NXP® level translators 74AVC16245DGG-Q100
- ロジック製品セレクションガイド... 74LVC_H_245A_Q100
- Logic selection guide 2016 74LVC_H_245A_Q100
- aup2g79 IBIS model 74AUP2G79GT
- plastic extremely thin small outline package; no leads; 8 terminals; body 3 x 2 x 0.5 mm 74AHC_T_3G14_Q100
- XSON8(U); Reel pack, Reverse; SMD, 7" Q3/T4 Standard product orientation Orderable part number ending ,125 or... 74AHC_T_3G14_Q100
- 74AUP2G79
- LM75B
