74HC112D: dual JK flip-flop with set and reset; negative-edge trigger
The 74HC112; 74HCT112 is a dual negative-edge triggered JK flip-flop. It features individual J and K inputs, clock (nCP) set (nSD) and reset (nRD) inputs. It also has complementary nQ and nQ outputs. The set and reset are asynchronous active LOW inputs and operate independently of the clock input. The J and K inputs control the state changes of the flip-flops as described in the mode select function table. The J and K inputs must be stable one set-up time prior to the HIGH-to-LOW clock transition for predictable operation. Inputs include clamp diodes that enable the use of current limiting resistors to interface inputs to voltages in excess of VCC.
Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times.
sot109-1_3d
Data Sheets (1)
| Name/Description | Modified Date |
|---|---|
| Dual JK flip-flop with set and reset; negative-edge trigger (REV 3.0) PDF (188.0 kB) 74HC_HCT112 [English] | 09 Aug 2016 |
Application Notes (2)
| Name/Description | Modified Date |
|---|---|
| Live Insertion Aspects of Philips Logic Families (REV 1.0) PDF (73.0 kB) AN252 [English] | 13 Mar 2013 |
| Pin FMEA 74HC/74HCT family (REV 1.0) PDF (51.0 kB) AN11044 [English] | 16 Mar 2011 |
Users Guides (1)
| Name/Description | Modified Date |
|---|---|
| HC/T User Guide (REV 1.0) PDF (508.0 kB) HCT_USER_GUIDE [English] | 01 Nov 1997 |
Package Information (1)
| Name/Description | Modified Date |
|---|---|
| plastic small outline package; 16 leads; body width 3.9 mm (REV 1.0) PDF (192.0 kB) SOT109-1 [English] | 08 Feb 2016 |
Supporting Information (2)
| Name/Description | Modified Date |
|---|---|
| Footprint for reflow soldering (REV 1.0) PDF (9.0 kB) SO-SOJ-REFLOW [English] | 08 Oct 2009 |
| Footprint for wave soldering (REV 1.0) PDF (8.0 kB) SO-SOJ-WAVE [English] | 08 Oct 2009 |
Ordering Information
| Product | Status | Family | Function | VCC (V) | Description | Logic switching levels | Package version | Output drive capability (mA) | tpd (ns) | fmax (MHz) | Power dissipation considerations | Tamb (Cel) | Rth(j-a) (K/W) | Ψth(j-top) (K/W) | Rth(j-c) (K/W) | Package name | No of pins |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 74HC112D | Active | HC(T) | J-K type flip-flops | 2.0 - 6.0 | negative-edge trigger | CMOS | SOT109-1 | +/- 5.2 | 15 | 66 | low | -40~125 | 76 | 2.4 | 34 | SO16 | 16 |
Package Information
| Product ID | Package Description | Outline Version | Reflow/Wave Soldering | Packing | Product Status | Part NumberOrdering code(12NC) | Marking | Chemical Content | RoHS / Pb Free / RHF | LeadFree Conversion Date | EFR | IFR(FIT) | MTBF(hour) | MSL | MSL LF |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 74HC112D | | SOT109-1 | SO-SOJ-REFLOW
SO-SOJ-WAVE SO-SOJ-REFLOW SO-SOJ-WAVE | Reel 13" Q1/T1 CECC | Active | 74HC112D,653 (9337 144 90653) | 74HC112D | 74HC112D |    | week 6, 2004 | 84.9 | 6.62 | 1.51E8 | 1 | 1 |
| Bulk Pack, CECC | Active | 74HC112D,652 (9337 144 90652) | 74HC112D | 74HC112D | | week 6, 2004 | 84.9 | 6.62 | 1.51E8 | 1 | 1 |
- Live Insertion Aspects of Philips Logic Families 74HC_T_245_Q100
- Pin FMEA 74HC/74HCT family 74HC_T_597_Q100
- HC/T User Guide 74HCU04PW
- plastic small outline package; 16 leads; body width 3.9 mm NPIC6C596A_Q100
- Footprint for reflow soldering NPIC6C596A_Q100
- Footprint for wave soldering NPIC6C596A_Q100
- SA614A
