74HC193PW: Presettable synchronous 4-bit binary up, down counter
The 74HC193; 74HCT193 is a 4-bit synchronous binary up/down counter.
Separate up/down clocks, CPU and CPD respectively, simplify operation. The outputs
change state synchronously with the LOW-to-HIGH transition of either clock input. If the
CPU clock is pulsed while CPD is held HIGH, the device will count up. If the CPD clock
is pulsed while CPU is held HIGH, the device will count down. Only one clock input can
be held HIGH at any time to guarantee predictable behavior. The device can be cleared at
any time by the asynchronous master reset input (MR); it may also be loaded in parallel
by activating the asynchronous parallel load input (PL).
The terminal count up (TCU) and terminal count down (TCD) outputs are normally HIGH. When the circuit has
reached the maximum count state of 15, the next HIGH-to-LOW transition of CPU will cause
TCU to go LOW. TCU will
stay LOW until CPU goes HIGH again, duplicating the count up clock. Likewise, the TCD output will go LOW when the circuit is in the zero
state and the CPD goes LOW. The terminal count outputs can be used as the clock input
signals to the next higher order circuit in a multistage counter, since they duplicate
the clock waveforms. Multistage counters will not be fully synchronous, since there is a
slight delay time difference added for each stage that is added. The counter may be
preset by the asynchronous parallel load capability of the circuit. Information present
on the parallel data inputs (D0 to D3) is loaded into the counter and appears on the
outputs (Q0 to Q3) regardless of the conditions of the clock inputs when the parallel
load (PL) input is LOW. A HIGH level on the master reset
(MR) input will disable the parallel load gates, override both clock inputs and set all
outputs (Q0 to Q3) LOW. If one of the clock inputs is LOW during and after a reset or
load operation, the next LOW-to-HIGH transition of that clock will be interpreted as a
legitimate signal and will be counted. Inputs include clamp diodes. This enables the use
of current limiting resistors to interface inputs to voltages in excess of
VCC.
74HC193PW: Product Block Diagram
74HC193PW: Block Diagram
Outline 3d SOT403-1
Data Sheets (1)
Application Notes (2)
Users Guides (1)
| Name/Description | Modified Date |
|---|
| HC/T User Guide (REV 1.0) PDF (508.0 kB) HCT_USER_GUIDE [English] | 01 Nov 1997 |
Package Information (1)
Packing (1)
Supporting Information (1)
Ordering Information
| Product | Status | Family | VCC (V) | Function | Description | Output drive capability (mA) | Logic switching levels | Package version | tpd (ns) | Power dissipation considerations | Tamb (Cel) | Rth(j-a) (K/W) | Ψth(j-top) (K/W) | Rth(j-c) (K/W) | Package name | No of pins |
|---|
| 74HC193PW | Active | HC(T) | 2.0 - 6.0 | Binary counters/timers | separate up/down clocks | +/- 5.2 | CMOS | SOT403-1 | 20 | low | -40~125 | 101 | 1.0 | 27 | TSSOP16 | 16 |
Package Information
| Product ID | Package Description | Outline Version | Reflow/Wave Soldering | Packing | Product Status | Part NumberOrdering code(12NC) | Marking | Chemical Content | RoHS / Pb Free / RHF | LeadFree Conversion Date | EFR | IFR(FIT) | MTBF(hour) | MSL | MSL LF |
|---|
| 74HC193PW | | SOT403-1 | SSOP-TSSOP-VSO-WAVE | Reel 13" Q1/T1 | Active | 74HC193PW,118
(9351 889 80118) | HC193 | 74HC193PW |    | week 10, 2005 | 84.9 | 6.62 | 1.51E8 | 1 | 1 |
| Bulk Pack | Active | 74HC193PW,112
(9351 889 80112) | HC193 | 74HC193PW | | week 10, 2005 | 84.9 | 6.62 | 1.51E8 | 1 | 1 |
