74LVC126ABQ: Quad buffer/line driver with 5 V tolerant input/outputs; 3-state
The 74LVC126A consists of four non-inverting buffers/line drivers with 3-state outputs, which are controlled by the output enable input (nOE). A LOW at nOE causes the outputs to assume a high-impedance OFF-state.
Inputs can be driven from either 3.3 V or 5 V devices. When disabled, up to 5.5 V can be applied to the outputs.
74LVC126ABQ: Product Block Diagram
sot762-1_3d
Data Sheets (1)
| Name/Description | Modified Date |
|---|---|
| Quad buffer/line driver with 5 V tolerant input/outputs; 3-state (REV 8.0) PDF (131.0 kB) 74LVC126A [English] | 08 Apr 2014 |
Application Notes (5)
| Name/Description | Modified Date |
|---|---|
| Sorting through the low voltage logic maze (REV 1.0) PDF (72.0 kB) AN10156 [English] | 13 Mar 2013 |
| Package lead inductance considerations in high-speed applications (REV 1.0) PDF (43.0 kB) AN212 [English] | 13 Mar 2013 |
| Pin FMEA for LVC family (REV 1.0) PDF (44.0 kB) AN11009 [English] | 04 Feb 2011 |
| Power considerations when using CMOS and BiCMOS logic devices (REV 1.0) PDF (100.0 kB) AN263 [English] | 05 Feb 2002 |
| Interfacing 3 Volt and 5 Volt Applications (REV 1.0) PDF (63.0 kB) AN240 [English] | 15 Sep 1995 |
Package Information (1)
| Name/Description | Modified Date |
|---|---|
| plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 14 terminals; body 2.5 x 3 x... (REV 1.0) PDF (187.0 kB) SOT762-1 [English] | 08 Feb 2016 |
Packing (1)
| Name/Description | Modified Date |
|---|---|
| Standard product orientation 12NC ending 115 (REV 3.0) PDF (108.0 kB) SOT762-1_115 [English] | 09 Apr 2013 |
IBIS Model
- lvc126a IBIS model (REV 1.0) ibs LVC126A 4/7/2013
SPICE model
- lvc Spice model (REV 1.0) ZIP LVC 5/7/2013
Ordering Information
| Product | Status | Family | VCC (V) | Function | Description | Logic switching levels | Package version | Output drive capability (mA) | fmax (MHz) | No of bits | tpd (ns) | Power dissipation considerations | Tamb (Cel) | Rth(j-a) (K/W) | Ψth(j-top) (K/W) | Rth(j-c) (K/W) | Package name | No of pins |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 74LVC126ABQ | Active | LVC | 1.2 - 3.6 | Buffers/inverters/drivers | quad buffer/line driver (3-state) | CMOS/LVTTL | SOT762-1 | +/- 24 | 175 | 4 | 2.4 | low | -40~125 | 107 | 21.9 | 75 | DHVQFN14 | 14 |
Package Information
| Product ID | Package Description | Outline Version | Reflow/Wave Soldering | Packing | Product Status | Part NumberOrdering code(12NC) | Marking | Chemical Content | RoHS / Pb Free / RHF | LeadFree Conversion Date | EFR | IFR(FIT) | MTBF(hour) | MSL | MSL LF |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 74LVC126ABQ | | SOT762-1 | Reel 7" Q1/T1 | Active | 74LVC126ABQ,115 (9352 740 82115) | VC126 | 74LVC126ABQ |    | Always Pb-free | 123.8 | 3.87 | 2.58E8 | 1 | 1 |
- Sorting through the low voltage logic maze 74LVC_H_245A_Q100
- Package lead inductance considerations in high-speed applications 74LVC_H_245A_Q100
- Pin FMEA for LVC family 74LVC1G123_Q100
- Power considerations when using CMOS and BiCMOS logic devices 74AHCT244PW
- Interfacing 3 Volt and 5 Volt Applications 74LVC377PW
- lvc126a IBIS model 74LVC126APW
- lvc Spice model 74LVC3G17GT
- plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 14 terminals; body 2.5 x 3 x... 74LV164_Q100
- Standard product orientation 12NC ending 115 74LV164_Q100
- 74LVC126A
- 74LV164
