74LVC16374ADGG: 16-bit edge-triggered D-type flip-flop; 5 V tolerant; 3-state
The 74LVC16374A and 74LVCH16374A are 16-bit edge-triggered flip-flops featuring separate D-type inputs with bus hold (74LVCH16374A only) for each flip-flop and 3-state outputs for bus oriented applications. It consists of two sections of eight positive edge-triggered flip-flops. A clock input (nCP) and an output enable (nOE) are provided for each octal.
The flip-flops will store the state of their individual D-inputs that meet the set-up and hold time requirements on the LOW-to-HIGH clock (CP) transition.
When pin nOE is LOW, the contents of the flip-flops are available at the outputs. When pin nOE is HIGH, the outputs go to the high-impedance OFF-state. Operation of input nOE does not affect the state of the flip-flops.
Inputs can be driven from either 3.3 V or 5 V devices. When disabled, up to 5.5 V can be applied to the outputs. These features allow the use of these devices in mixed 3.3 V and 5 V applications.
Bus hold on data inputs eliminates the need for external pull-up resistors to hold unused inputs.
Outline 3d SOT362-1
Data Sheets (1)
| Name/Description | Modified Date |
|---|---|
| 16-bit edge-triggered D-type flip-flop; 5 V tolerant; 3-state (REV 11.0) PDF (138.0 kB) 74LVC_LVCH16374A [English] | 16 Jan 2013 |
Application Notes (5)
| Name/Description | Modified Date |
|---|---|
| Sorting through the low voltage logic maze (REV 1.0) PDF (72.0 kB) AN10156 [English] | 13 Mar 2013 |
| Package lead inductance considerations in high-speed applications (REV 1.0) PDF (43.0 kB) AN212 [English] | 13 Mar 2013 |
| Pin FMEA for LVC family (REV 1.0) PDF (44.0 kB) AN11009 [English] | 04 Feb 2011 |
| Power considerations when using CMOS and BiCMOS logic devices (REV 1.0) PDF (100.0 kB) AN263 [English] | 05 Feb 2002 |
| Interfacing 3 Volt and 5 Volt Applications (REV 1.0) PDF (63.0 kB) AN240 [English] | 15 Sep 1995 |
Package Information (1)
| Name/Description | Modified Date |
|---|---|
| plastic thin shrink small outline package; 48 leads; body width 6.1 mm (REV 1.0) PDF (467.0 kB) SOT362-1 [English] | 08 Feb 2016 |
Packing (1)
| Name/Description | Modified Date |
|---|---|
| TSSOP48; Reel pack; SMD, 13" Q1/T1 Standard product orientation Orderable part number ending ,118 or... (REV 5.0) PDF (242.0 kB) SOT362-1_118 [English] | 15 Apr 2013 |
Supporting Information (1)
| Name/Description | Modified Date |
|---|---|
| Footprint for wave soldering (REV 1.0) PDF (16.0 kB) SSOP-TSSOP-VSO-WAVE [English] | 08 Oct 2009 |
IBIS Model
- lvc163 IBIS model (REV 1.0) ibs LVC163 4/7/2013
- lvc16374a IBIS model (REV 1.0) ibs LVC16374A 4/7/2013
Ordering Information
| Product | Status | Family | Function | VCC (V) | Logic switching levels | Description | Output drive capability (mA) | Package version | tpd (ns) | fmax (MHz) | Power dissipation considerations | Tamb (Cel) | Rth(j-a) (K/W) | Ψth(j-top) (K/W) | Rth(j-c) (K/W) | Package name | No of pins |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 74LVC16374ADGG | Active | LVC | D-type flip-flops | 1.2 - 3.6 | CMOS/LVTTL | positive-edge trigger (3-state) | +/- 24 | SOT362-1 | 3.8 | 150 | low | -40~125 | 82 | 2.0 | 37 | TSSOP48 | 48 |
Package Information
| Product ID | Package Description | Outline Version | Reflow/Wave Soldering | Packing | Product Status | Part NumberOrdering code(12NC) | Marking | Chemical Content | RoHS / Pb Free / RHF | LeadFree Conversion Date | EFR | IFR(FIT) | MTBF(hour) | MSL | MSL LF |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 74LVC16374ADGG | | SOT362-1 | SSOP-TSSOP-VSO-WAVE | Bulk Pack | Active | 74LVC16374ADGG,112 (9352 351 90112) | LVC16374A | 74LVC16374ADGG |    | Always Pb-free | 123.8 | 3.87 | 2.58E8 | 1 | 1 |
| Reel 13" Q1/T1 | Active | 74LVC16374ADGG,118 (9352 351 90118) | LVC16374A | 74LVC16374ADGG | | Always Pb-free | 123.8 | 3.87 | 2.58E8 | 1 | 1 | ||||
| Tube in Drypack | Withdrawn | 74LVC16374ADGG,512 (9352 351 90512) | LVC16374A | 74LVC16374ADGG |  | week 14, 2005 | 123.8 | 3.87 | 2.58E8 | 2 | 2 |
- Sorting through the low voltage logic maze 74LVC_H_245A_Q100
- Package lead inductance considerations in high-speed applications 74LVC_H_245A_Q100
- Pin FMEA for LVC family 74LVC1G123_Q100
- Power considerations when using CMOS and BiCMOS logic devices 74AHCT244PW
- Interfacing 3 Volt and 5 Volt Applications 74LVC377PW
- lvc163 IBIS model 74LVC163PW
- lvc16374a IBIS model 74LVC16374ADL
- plastic thin shrink small outline package; 48 leads; body width 6.1 mm 74LVC_H_16245A_Q100
- SSOP-TSSOP-VSO-WAVE LPC1114FDH28
- TSSOP48; Reel pack; SMD, 13" Q1/T1 Standard product orientation Orderable part number ending ,118 or... 74LVC_H_16245A_Q100
- 74LVTN16245B
