74LVT573DB: 3.3 V octal D-type transparent latch; 3-state

The 74LVT573 is a high-performance BiCMOS product designed for VCC operation at 3.3 V. This device is an octal transparent latch coupled to eight 3-state output buffers. The two sections of the device are controlled independently by Latch Enable (LE) and Output Enable (OE) control gates. The 74LVT573 has a broadside pinout configuration to facilitate PC board layout and allow easy interface with microprocessors.

The data on the Dn inputs are transferred to the latch outputs when the Latch Enable (LE) input is High. The latch remains transparent to the data inputs while LE is High, and stores the data that is present one setup time before the High-to-Low enable transition.

The 3-state output buffers are designed to drive heavily loaded 3-state buses, MOS memories, or MOS microprocessors. The active-Low Output Enable (OE) controls all eight 3-state buffers independent of the latch operation.

When OE is Low, the latched or transparent data appears at the outputs. When OE is High, the outputs are in the High-impedance “OFF” state, which means they will neither drive nor load the bus.

74LVT573DB: Product Block Diagram
74LVT573DB: Block Diagram
74LVT573DB: Block Diagram
74LVT573DB: Block Diagram
74LVT573DB: Block Diagram
Outline 3d SOT339-1
Data Sheets (1)
Name/DescriptionModified Date
3.3 V octal D-type transparent latch; 3-state (REV 8.0) PDF (317.0 kB) 74LVT573 [English]15 Dec 2011
Application Notes (8)
Name/DescriptionModified Date
Sorting through the low voltage logic maze (REV 1.0) PDF (72.0 kB) AN10156 [English]13 Mar 2013
Package lead inductance considerations in high-speed applications (REV 1.0) PDF (43.0 kB) AN212 [English]13 Mar 2013
A metastability primer (REV 1.0) PDF (40.0 kB) AN219 [English]13 Mar 2013
Ground and VCC Bounce of High-Speed Integrated Circuits (REV 1.0) PDF (25.0 kB) AN223 [English]13 Mar 2013
Live Insertion Aspects of Philips Logic Families (REV 1.0) PDF (73.0 kB) AN252 [English]13 Mar 2013
Test Fixtures for High Speed Logic (REV 1.0) PDF (341.0 kB) AN203 [English]02 Apr 1998
Transmission Lines and Terminations with Philips Advanced Logic Families (REV 1.0) PDF (217.0 kB) AN246 [English]01 Feb 1998
LVT (Low Voltage Technology) and ALVT (Advanced LVT) (REV 1.0) PDF (133.0 kB) AN243 [English]01 Jan 1998
Selector Guides (2)
Name/DescriptionModified Date
ロジック製品セレクションガイド... (REV 1.0) PDF (38.3 MB) LOGIC_SELECTION_GUIDE_2015_JP [English]19 Nov 2015
Logic selection guide 2016 (REV 1.1) PDF (15.3 MB) 75017285 [English]08 Jan 2015
Package Information (1)
Name/DescriptionModified Date
plastic shrink small outline package; 20 leads; body width 5.3 mm (REV 1.0) PDF (325.0 kB) SOT339-1 [English]08 Feb 2016
Packing (1)
Name/DescriptionModified Date
SSOP20; Reel pack; SMD, 13" Q1/T1 Standard product orientation Orderable part number ending ,118 or J Ordering code... (REV 1.0) PDF (204.0 kB) SOT339-1_118 [English]02 Oct 2015
Supporting Information (1)
Name/DescriptionModified Date
Footprint for wave soldering (REV 1.0) PDF (16.0 kB) SSOP-TSSOP-VSO-WAVE [English]08 Oct 2009
IBIS Model
SPICE model
Ordering Information
ProductStatusFamilyFunctionVCC (V)Logic switching levelsDescriptionOutput drive capability (mA)Package versiontpd (ns)No of bitsPower dissipation considerationsTamb (Cel)Rth(j-a) (K/W)Ψth(j-top) (K/W)Rth(j-c) (K/W)Package nameNo of pins
74LVT573DBActiveLVTLatches/registered drivers2.7 - 3.6TTLoctal D-type transparent latch (3-state)-32/+64SOT339-12.78medium-40~8513640.0SSOP2020
Package Information
Product IDPackage DescriptionOutline VersionReflow/Wave SolderingPackingProduct StatusPart NumberOrdering code(12NC)MarkingChemical ContentRoHS / Pb Free / RHFLeadFree Conversion DateEFRIFR(FIT)MTBF(hour)MSLMSL LF
74LVT573DBSOT339-1SSOP-TSSOP-VSO-WAVEReel 13" Q1/T1Active74LVT573DB,118 (9351 707 10118)LVT57374LVT573DBweek 13, 200570.81.337.52E811
Bulk PackActive74LVT573DB,112 (9351 707 10112)LVT57374LVT573DBweek 13, 200570.81.337.52E811
3.3 V octal D-type transparent latch; 3-state 74LVT573PW
Sorting through the low voltage logic maze 74LVC_H_245A_Q100
Package lead inductance considerations in high-speed applications 74LVC_H_245A_Q100
A metastability primer 74AHC573PW
Ground and VCC Bounce of High-Speed Integrated Circuits 74ALVC164245DGG-Q100
Live Insertion Aspects of Philips Logic Families 74HC_T_245_Q100
Test Fixtures for High Speed Logic 74ABTH162245ADL
Transmission Lines and Terminations with Philips Advanced Logic Families 74LVTN16245BDGG
LVT (Low Voltage Technology) and ALVT (Advanced LVT) 74LVTN16245BDGG
ロジック製品セレクションガイド... 74LVC_H_245A_Q100
Logic selection guide 2016 74LVC_H_245A_Q100
lvt573 IBIS model 74LVT573PW
lvt Spice model 74LVT640PW
plastic shrink small outline package; 20 leads; body width 5.3 mm 74LVC373A_Q100
SSOP-TSSOP-VSO-WAVE LPC1114FDH28
SSOP20; Reel pack; SMD, 13" Q1/T1 Standard product orientation Orderable part number ending ,118 or J Ordering code... 74LVC373A_Q100
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