74VHC595D: 8-bit serial-in_serial-out or parallel-out shift register
The 74VHC595; 74VHCT595 are high-speed Si-gate CMOS devices and are pin
compatible with Low-power Schottky TTL (LSTTL). It is specified in compliance with
JEDEC standard No. 7A.
The 74VHC595; 74VHCT595 are 8-stage serial shift registers with a storage register and
3-state outputs. The shift registers have separate clocks.
Data is shifted on the positive-going transitions of the shift register clock input (SHCP).
The data in each register is transferred to the storage register on a positive-going
transition of the storage register clock input (STCP). If both clocks are connected together,
the shift register will always be one clock pulse ahead of the storage register.
The shift register has a serial input (DS) and a serial standard output (Q7S) for cascading.
It is also provided with asynchronous reset (active LOW) for all 8 shift register stages. The
storage register has 8 parallel 3-state bus driver outputs. Data in the storage register
appears at the output whenever the output enable input (OE) is LOW.
sot109-1_3d
Data Sheets (1)
Package Information (1)
Packing (1)
Supporting Information (2)
IBIS Model
Ordering Information
| Product | Status | Family | VCC (V) | Function | Logic switching levels | Description | Output drive capability (mA) | Package version | tpd (ns) | fmax (MHz) | No of bits | Power dissipation considerations | Tamb (Cel) | Rth(j-a) (K/W) | Ψth(j-top) (K/W) | Rth(j-c) (K/W) | Package name | No of pins |
|---|
| 74VHC595D | Active | VHC(T) | 2.0 - 5.5 | Shift registers | CMOS | 8-bit serial-in/parallel-out shift register with output storage register (3-state) | +/- 8 | SOT109-1 | 4 | 170 | 8 | low | -40~125 | 90 | 8.3 | 49 | SO16 | 16 |
Package Information
