74VHCT125D: Quad buffer/line driver; 3-state
The 74VHC125; 74VHCT125 are high-speed Si-gate CMOS devices and are pin compatible with Low-power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard JESD7-A.
The 74VHC125; 74VHCT125 provides four non-inverting buffer/line drivers with 3-state outputs. The 3-state outputs (nY) are controlled by the output enable input (nOE). A HIGH at nOE causes the outputs to assume a high-impedance OFF-state.
The 74VHC125; 74VHCT125 are identical to the 74VHC126; 74VHCT126 but have active LOW enable inputs.
74VHCT125D: Product Block Diagram
sot108-1_3d
Data Sheets (1)
Selector Guides (2)
Package Information (1)
Packing (1)
Supporting Information (2)
IBIS Model
Ordering Information
Product | Status | Family | Function | VCC (V) | Logic switching levels | Description | Output drive capability (mA) | Package version | fmax (MHz) | No of bits | tpd (ns) | Power dissipation considerations | Tamb (Cel) | Rth(j-a) (K/W) | Ψth(j-top) (K/W) | Rth(j-c) (K/W) | Package name | No of pins |
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74VHCT125D | Active | VHC(T) | Buffers/inverters/drivers | 4.5 - 5.5 | TTL | quad buffer/line driver (3-state) | +/- 8 | SOT108-1 | 60 | 4 | 3 | low | -40~125 | 127 | 18.2 | | SO14 | 14 |
Package Information