74AUP1G374GW-Q100: Low-power D-type flip-flop; positive-edge trigger; 3-state
The 74AUP1G374-Q100 provides the single D-type flip-flop with 3-state output. The flip-flop stores the state of data input (D) that meets the set-up and hold times requirements on the LOW-to-HIGH CP transition. When pin OE is LOW, the contents of the flip-flop is available at the (Q) output. When pin OE is HIGH, the output goes to the high-impedance OFF-state. Operation of input pin OE does not affect the state of the flip-flop.
Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire VCC range from 0.8 V to 3.6 V. This device ensures a very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V.
This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down.
This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications.
74AUP1G374GW-Q100: Product Block Diagram
SOT363
Data Sheets (1)
| Name/Description | Modified Date |
|---|---|
| Low-power D-type flip-flop; positive-edge trigger; 3-state (REV 1.0) PDF (126.0 kB) 74AUP1G374_Q100 | 19 Feb 2013 |
Application Notes (2)
| Name/Description | Modified Date |
|---|---|
| Sorting through the low voltage logic maze (REV 1.0) PDF (72.0 kB) AN10156 | 13 Mar 2013 |
| Pin FMEA for AUP family (REV 1.0) PDF (53.0 kB) AN11052 | 06 May 2011 |
Brochures (3)
| Name/Description | Modified Date |
|---|---|
| 電圧レベルシフタ (REV 1.1) PDF (3.1 MB) 75017511_JP | 16 Feb 2015 |
| NXP® ultra-low-power CMOS logic 74AUP1G/2G/3Gxxx: Advanced, ultra-low-power CMOS logic (REV 1.0) PDF (1.4 MB) 75017458 | 13 Oct 2014 |
| Voltage translation: How to manage mixed-voltage designs with NXP® level translators (REV 1.0) PDF (2.6 MB) 75017511 | 20 May 2014 |
Selector Guides (2)
| Name/Description | Modified Date |
|---|---|
| ロジック製品セレクションガイド... (REV 1.0) PDF (38.3 MB) LOGIC_SELECTION_GUIDE_2015_JP | 19 Nov 2015 |
| Logic selection guide 2016 (REV 1.1) PDF (15.3 MB) 75017285 | 08 Jan 2015 |
Package Information (1)
| Name/Description | Modified Date |
|---|---|
| plastic surface-mounted package; 6 leads (REV 1.0) PDF (246.0 kB) SOT363_1 | 08 Feb 2016 |
Packing (1)
| Name/Description | Modified Date |
|---|---|
| Tape reel SMD; reversed product orientation 12NC ending 125 (REV 1.0) PDF (188.0 kB) SOT363_125 | 20 Nov 2012 |
Supporting Information (3)
| Name/Description | Modified Date |
|---|---|
| Reflow Soldering Profile (REV 1.0) PDF (34.0 kB) REFLOW_SOLDERING_PROFILE | 30 Sep 2013 |
| Wave Soldering Profile (REV 1.0) PDF (20.0 kB) WAVE_SOLDERING_PROFILE | 30 Sep 2013 |
| MAR_SOT363 Topmark (REV 1.0) PDF (104.0 kB) MAR_SOT363 | 03 Jun 2013 |
Ordering Information
| Product | Status | VCC (V) | Family | Description | Logic switching levels | Output drive capability (mA) | tpd (ns) | fmax (MHz) | Power dissipation considerations | Tamb (Cel) | Rth(j-a) (K/W) | Ψth(j-top) (K/W) | Rth(j-c) (K/W) | Package name | No of pins | Package version |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 74AUP1G374GW-Q100 | Active | 1.1 - 3.6 | AUP | single D-type flip-flop | CMOS | +/- 1.9 | 7.9 | 400 | ultra low | -40~125 | 264 | 38.6 | 153 | TSSOP6 | 6 | SOT363 |
Package Information
| Product ID | Package Description | Outline Version | Reflow/Wave Soldering | Packing | Product Status | Part NumberOrdering code(12NC) | Marking | Chemical Content | RoHS / Pb Free / RHF | LeadFree Conversion Date | MSL | MSL LF |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 74AUP1G374GW-Q100 | | SOT363 | Reflow_Soldering_Profile
Wave_Soldering_Profile Reflow_Soldering_Profile Wave_Soldering_Profile | Reel 7" Q3/T4, Reverse | Active | 74AUP1G374GW-Q100H (9353 002 12125) | aX | 74AUP1G374GW-Q100 |    | Always Pb-free | 1 | 1 |
