74HC237D-Q100: 3-to-8 line decoder, demultiplexer with address latches
The 74HC237-Q100 is a 3-to-8 line decoder, demultiplexer with latches at the three
address inputs (An). The 74HC237-Q100 essentially combines the 3-to-8 decoder
function with a 3-bit storage latch. When the latch is enabled (LE = LOW), the
74HC237-Q100 acts as a 3-to-8 active LOW decoder. When the latch enable (LE) goes
from LOW-to-HIGH, the last data present at the inputs before this transition, is stored in
the latches. Further address changes are ignored as long as LE remains HIGH. The
output enable input (E1 and E2) controls the state of the outputs independent of the
address inputs or latch operation. All outputs are HIGH unless E1 is LOW and E2 is HIGH.
The 74HC237-Q100 is ideally suited for implementing non-overlapping decoders in
3-state systems and strobed (stored address) applications in bus-oriented systems.
This product has been qualified to the Automotive Electronics Council (AEC) standard
Q100 (Grade 1) and is suitable for use in automotive applications.
sot109-1_3d
Data Sheets (1)
Application Notes (1)
Package Information (1)
Packing (1)
Supporting Information (2)
Ordering Information
| Product | Status | Family | VCC (V) | Logic switching levels | Description | Output drive capability (mA) | tpd (ns) | Power dissipation considerations | Tamb (Cel) | Rth(j-a) (K/W) | Ψth(j-top) (K/W) | Rth(j-c) (K/W) | Package name | No of pins | Package version |
|---|
| 74HC237D-Q100 | Active | HC(T) | 2.0 - 6.0 | CMOS | 3-to-8 decoder/demultiplexer with address latches | +/- 5.2 | 18 | low | -40~125 | 71 | 1.0 | 29 | SO16 | 16 | SOT109-1 |
Package Information
