HEF4020BT-Q100: 14-stage binary counter
The HEF4020B-Q100 is a 14-stage binary counter with a clock input (CP), an overriding
asynchronous master reset input (MR) and twelve fully buffered outputs (Q0, and Q3 to
Q13). The counter advances on the HIGH to LOW transition of CP. A HIGH on MR clears
all counter stages and forces all outputs LOW, independent of the state of CP. Each
counter stage is a static toggle flip-flop. A feature of the device is its high speed
(typ. 35 MHz at VDD = 15 V).
It operates over a recommended VDD power supply range of 3 V to 15 V referenced to VSS
(usually ground). Unused inputs must be connected to VDD, VSS, or another input.
This product has been qualified to the Automotive Electronics Council (AEC) standard
Q100 (Grade 3) and is suitable for use in automotive applications.
sot109-1_3d
Data Sheets (1)
Brochures (2)
Package Information (1)
Packing (1)
Supporting Information (2)
Ordering Information
| Product | Status | Family | VCC (V) | Output drive capability (mA) | Description | Logic switching levels | tpd (ns) | fmax (MHz) | Power dissipation considerations | Tamb (Cel) | Rth(j-a) (K/W) | Ψth(j-top) (K/W) | Rth(j-c) (K/W) | Package name | No of pins | Package version |
|---|
| HEF4020BT-Q100 | Active | HEF4000B | 4.5 - 15.5 | +/- 2.4 | 14-stage binary counter | CMOS | 30 | 18 | medium | -40~85 | 56 | 1.0 | 13 | SO16 | 16 | SOT109-1 |
Package Information
