HEF4027B: Dual JK flip-flop (Based on PIP HEF4027B)
The HEF4027B is a edge-triggered dual JK flip-flop which features independent set-direct (SD), clear-direct (CD), clock (CP) inputs and outputs (Q, Q). Data is accepted when CP is LOW, and transferred to the output on the positive-going edge of the clock. The active HIGH asynchronous clear-direct (CD) and set-direct (SD) inputs are independent and override the J, K, and CP inputs. The outputs are buffered for best system performance. Schmitt trigger action makes the clock input highly tolerant of slower rise and fall times.
It operates over a recommended VDD power supply range of 3 V to 15 V referenced to VSS (usually ground). Unused inputs must be connected to VDD, VSS, or another input.
sot109-1_3d
Data Sheets (1)
| Name/Description | Modified Date |
|---|
| Dual JK flip-flop (REV 10.0) PDF (139.0 kB) HEF4027B [English] | 21 Mar 2016 |
Application Notes (1)
Brochures (2)
Package Information (1)
Supporting Information (2)
Ordering Information
| Product | Status |
|---|
| HEF4027BT | Active |
Package Information
| Product ID | Package Description | Outline Version | Reflow/Wave Soldering | Packing | Product Status | Part NumberOrdering code(12NC) | Marking | Chemical Content | RoHS / Pb Free / RHF | LeadFree Conversion Date | EFR | IFR(FIT) | MTBF(hour) | MSL | MSL LF |
|---|
| HEF4027BT | | SOT109-1 | SO-SOJ-REFLOW
SO-SOJ-WAVE
SO-SOJ-REFLOW
SO-SOJ-WAVE | Reel 13" Q1/T1 CECC | Active | HEF4027BT,653
(9333 727 90653) | HEF4027BT | HEF4027BT |    | week 6, 2004 | 75.3 | 2.99 | 3.34E8 | 1 | 1 |
| Bulk Pack, CECC | Active | HEF4027BT,652
(9333 727 90652) | HEF4027BT | HEF4027BT | | week 6, 2004 | 75.3 | 2.99 | 3.34E8 | 1 | 1 |
