HEF4094BTS: 8-stage shift-and-store register
The HEF4094B is an 8-stage serial shift register. It has a storage latch associated with
each stage for strobing data from the serial input to parallel buffered 3‑state outputs
QP0 to QP7. The parallel outputs may be connected directly to common bus lines. Data is
shifted on positive‑going clock transitions. The data in each shift register stage is
transferred to the storage register when the strobe (STR) input is HIGH. Data in the
storage register appears at the outputs whenever the output enable (OE) signal is HIGH.
Two serial outputs (QS1 and QS2) are available for cascading a number of HEF4094B
devices. Serial data is available at QS1 on positive‑going clock edges to allow high‑speed
operation in cascaded systems with a fast clock rise time. The same serial data is
available at QS2 on the next negative going clock edge. This is used for cascading
HEF4094B devices when the clock has a slow rise time.
It operates over a recommended VDD power supply range of 3 V to 15 V referenced to VSS
(usually ground). Unused inputs must be connected to VDD, VSS, or another input.
HEF4094BTS: Product Block Diagram
Outline 3d SOT338-1
Data Sheets (1)
Application Notes (1)
Brochures (2)
Package Information (1)
Supporting Information (2)
Ordering Information
| Product | Status | Family | VCC (V) | Function | Description | Logic switching levels | Output drive capability (mA) | Package version | tpd (ns) | fmax (MHz) | No of bits | Power dissipation considerations | Tamb (Cel) | Rth(j-a) (K/W) | Ψth(j-top) (K/W) | Rth(j-c) (K/W) | Package name | No of pins |
|---|
| HEF4094BTS | Active | HEF4000B | 4.5 - 15.5 | Shift registers | 8-bit serial-in/serial or parallel-out shift register with output register (3-state) | CMOS | +/- 2.4 | SOT338-1 | 50 | 28 | 8 | medium | -40~85 | 148 | 42.0 | | SSOP16 | 16 |
Package Information
