LPC11A12FHN33: Scalable Entry Level 32-bit Microcontroller (MCU) based on ARM® Cortex®-M0+/M0 Cores
The LPC11A12FHN33 is an ARM Cortex-M0 based, low-cost 32-bit microcontroller, designed for 8/16-bit microcontroller applications, offering performance, low power, simple instruction set and memory addressing together with reduced code size compared to existing 8/16-bit architectures. The LPC11A12FHN33 operates at CPU frequencies of up to 50 MHz. Analog/mixed-signal subsystems can be configured by software from interconnected digital and analog peripherals.
sot865-3_3d
Data Sheets (2)
| Name/Description | Modified Date |
|---|---|
| 32-bit ARM Cortex-M0 microcontroller; up to 32 kB flash, 8 kB SRAM, 4 kB EEPROM; configurable analog/mixed-signal (REV 1.1) PDF (2.6 MB) LPC11AXX_ZH_1 | 20 May 2016 |
| 32-bit ARM Cortex-M0 microcontroller; up to 32 kB flash, 8 kB SRAM, 4 kB EEPROM; configurable analog/mixed-signal (REV 4.0) PDF (1.8 MB) LPC11AXX | 30 Oct 2012 |
Errata (1)
| Name/Description | Modified Date |
|---|---|
| Errata sheet LPC11Axx (REV 2.0) PDF (38.0 kB) ES_LPC11AXX | 17 Jan 2013 |
Application Notes (9)
| Name/Description | Modified Date |
|---|---|
| AES encryption and decryption software on LPC microcontrollers (REV 1.1) ZIP (174.0 kB) AN11241 | 17 Mar 2014 |
| In-Application Programming for the LPC11Axx (REV 1.0) ZIP (979.0 kB) AN11387 | 13 Aug 2013 |
| Using LPC11Axx EEPROM (with IAP) (REV 2.0) ZIP (147.0 kB) AN11073 | 09 Aug 2013 |
| Frequency counter using the analog comparator of the LPC11Axx (REV 1.0) ZIP (567.0 kB) AN11242 | 09 Aug 2013 |
| I2C secondary boot loader (REV 1.0) ZIP (661.0 kB) AN11258 | 09 Aug 2013 |
| How to implement the ROM I2C (REV 1.0) ZIP (890.0 kB) AN11249 | 22 Jul 2013 |
| SPI secondary boot loader (REV 1.0) ZIP (638.0 kB) AN11257 | 22 Jul 2013 |
| How to implement the PMBus software stack (REV 1.0) ZIP (1.1 MB) AN11318 | 22 Jul 2013 |
| UUencoding for UART ISP (REV 1.0) PDF (139.0 kB) AN11229 | 06 Jul 2012 |
Users Guides (2)
| Name/Description | Modified Date |
|---|---|
| LPC11Axx User manual (REV 5.0) PDF (2.5 MB) UM10527 | 23 Jan 2013 |
| LPC11Axx User manual (REV 1.0) PDF (3.7 MB) UM10527_ZH | 28 Aug 2012 |
Brochures (1)
| Name/Description | Modified Date |
|---|---|
| NXP® 50 MHz, 32-bit Cortex TM-M0 MCUs LPC11A00 (REV 1.0) PDF (729.0 kB) 75017092 | 01 Jun 2012 |
Package Information (1)
| Name/Description | Modified Date |
|---|---|
| plastic thermal enhanced very thin quad flat package; no leads; 32 terminals; body 7 x 7 x 0.85 mm (REV 1.0) PDF (204.0 kB) SOT865-3 | 08 Feb 2016 |
Supporting Information (1)
| Name/Description | Modified Date |
|---|---|
| ADC design guidelines (REV 1.0) PDF (145.0 kB) TN00009 | 09 May 2014 |
Ordering Information
| Product | Status | Core | Clock speed [max] (MHz) | DMIPS | Flash (kB) | RAM (kB) | EEPROM (kB) | GPIO | Ethernet | USB | USB (speed) | USB (type) | LCD | CAN | DAC (bits) | UART | I²C | SPI | I²S | ADC sample rate | ADC channels | ADC (bits) | Comparators | Timers | Timer (bits) | SCTimer / PWM | RTC | PWM | Package name | Temperature range | Temperature sensor | IOH | Supply voltage [min] (V) | Supply voltage [max] (V) | Product category | Demoboard |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| LPC11A12FHN33/101 | Active | Cortex-M0 | 50 | 16 | 4 | 1 | 28 | 10 | 1 | 1 | 2 | 8 | 10 | 1 | 4 | 16; 32 | 1 | 11 | HVQFN32 | -40 °C to +85 °C | 1 | 1.8 | 3.6 | OM13025 |
Package Information
| Product ID | Package Description | Outline Version | Reflow/Wave Soldering | Packing | Product Status | Part NumberOrdering code(12NC) | Marking | Chemical Content | RoHS / Pb Free / RHF | LeadFree Conversion Date | MSL | MSL LF |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| LPC11A12FHN33/101 | | SOT865-3 | Tray, Bakeable, Single in Drypack | Active | LPC11A12FHN33/101, (9352 939 75551) | Standard Marking | LPC11A12FHN33/101 |    | Always Pb-free | 3 | 3 |
- 32-bit ARM Cortex-M0 microcontroller; up to 32 kB flash, 8 kB SRAM, 4 kB EEPROM; configurable analog/mixed-signal LPC11A14FHN33
- Errata sheet LPC11Axx LPC11A14FHN33
- AES encryption and decryption software on LPC microcontrollers LPC43S50FET256
- In-Application Programming for the LPC11Axx LPC11A14JBD48
- Using LPC11Axx EEPROM (with IAP) LPC11A14FHN33
- Frequency counter using the analog comparator of the LPC11Axx LPC11A14FHN33
- I2C secondary boot loader LPC1788FET208
- How to implement the ROM I2C LPC11A14FHN33
- SPI secondary boot loader LPC1788FET208
- How to implement the PMBus software stack LPC43S50FET256
- UUencoding for UART ISP LPC43S50FET256
- LPC11Axx User manual LPC11A14FHN33
- LPC11Axx User manual LPC11A14FHN33
- NXP® 50 MHz, 32-bit Cortex TM-M0 MCUs LPC11A00 LPC11A14FHN33
- ADC design guidelines LPC4333JET256
- SOT865-3 LPC1347FHN33
- NXQ1TXA1
