MC100ELT28: Translator, TTL to Differential PECL and Differential PECL to TTL

The MC10ELT/100ELT28 is a differential PECL to TTL translator and a TTL to differential PECL translator in a single package. Because PECL (Positive ECL) levels are used, only +5 V and ground are required. The small outline 8-lead package and the dual translation design of the ELT28 makes it ideal for applications which are sending and receiving signals across a backplane.The 100 Series contains temperature compensation.

Features
  • 3.5ns Typical PECL to TTL Propagation Delay
  • 1.2ns Typical TTL to PECL Propagation Delay
  • PNP TTL Inputs for Minimal Loading
  • 24mA TTL Outputs
  • Flow Through Pinouts
  • ESD Protection: > 2 KV HBM
  • Operating Range VCC= 4.75 V to 5.25 V with GND= 0 V
  • QTTL Output Will Default High with Inputs Left Open or < 1.3 V
  • QECL Output Will Default High with Inputs Left Open
  • Internal PECL Input Pulldown Resistors
  • Internal PECL Input Pulldown Resistors
  • Moisture Sensitivity Level 1For Additional Information, see Application Note AND8003/D
  • Flammability Rating: UL-94 code V-0 @ 1/8", Oxygen Index 28 to 34
  • Transistor Count = 71 devices
  • Pb-Free Packages are Available
Application Notes (17)
Document TitleDocument ID/SizeRevisionRevision Date
AC Characteristics of ECL DevicesAND8090/D (896.0kB)1
Clock Generation and Clock and Data Marking and Ordering Information GuideAND8002/D (71kB)12
Clock Management Design Using Low Skew and Low Jitter DevicesTND301/D (205.0kB)0
Designing with PECL (ECL at +5.0 V)AN1406/D (105.0kB)2
ECL Clock Distribution TechniquesAN1405/D (54.0kB)1
ECLinPS Lite Translator ELT Family SPICE I/O Model KitAN1596/D (189.0kB)2
ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information GuideAND8002 (71kB)12
Interfacing Between LVDS and ECLAN1568/D (121.0kB)11
Interfacing with ECLinPSAND8066/D (72kB)3
Metastability and the ECLinPS FamilyAN1504/D (103.0kB)3
Odd Number Divide By Counters with 50% Outputs and Synchronous ClocksAND8001/D (90.0kB)0
Phase Lock Loop General OperationsAND8040/D (64.0kB)3
Storage and Handling of Drypack Surface Mount DeviceAND8003/D (49kB)2Mar, 2016
Termination of ECL Logic DevicesAND8020/D (176.0kB)6
The ECL Translator GuideAN1672/D (142.0kB)12
Thermal Analysis and Reliability of WIRE BONDED ECLAND8072/D (119.0kB)5
Using Wire-OR Ties in ECLInPS™ DesignsAN1650/D (1130.0kB)3
Data Sheets (1)
Document TitleDocument ID/SizeRevisionRevision Date
Translator, TTL to Differential PECL and Differential PECL to TTLMC10ELT28/D (82kB)11
Simulation Models (2)
Document TitleDocument ID/SizeRevisionRevision Date
IBIS Model for MC100ELT28DMC100ELT28D.IBS (8.0kB)1
IBIS Model for MC100ELT28DTMC100ELT28DT.IBS (8.0kB)1
Package Drawings (2)
Document TitleDocument ID/SizeRevision
SOIC-8 Narrow Body751-07 (62.6kB)AK
TSSOP 8 3.0x3.0x0.95 mm948R-02 (77.3kB)A
Order Information
ProductStatusCompliancePackageMSL*ContainerBudgetary Price/Unit
MC100ELT28DGActivePb-free Halide freeSOIC-8751-071Tube98Contact BDTIC
MC100ELT28DR2GActivePb-free Halide freeSOIC-8751-071Tape and Reel2500Contact BDTIC
MC100ELT28DTGActivePb-free Halide freeTSSOP-8948R-023Tube100Contact BDTIC
MC100ELT28DTR2GLast ShipmentsPb-free Halide freeTSSOP-8948R-023Tape and Reel2500
Specifications
ProductChannelsInput LevelOutput LevelVCC Typ (V)fMax Typ (MHz)tpd Typ (ns)tR & tF Max (ps)
MC100ELT28DG2TTL ECLTTL ECL51001.21.1 1.6
MC100ELT28DR2G2TTL ECLTTL ECL51001.21.6 1.1
MC100ELT28DTG2TTL ECLTTL ECL51001.21.6 1.1
Translator, TTL to Differential PECL and Differential PECL to TTL (82kB) MC10ELT28
AC Characteristics of ECL Devices NB100LVEP91
Clock Generation and Clock and Data Marking and Ordering Information Guide NB100LVEP91
Clock Management Design Using Low Skew and Low Jitter Devices MC10H604
Designing with PECL (ECL at +5.0 V) NB100LVEP91
ECL Clock Distribution Techniques NB100LVEP91
ECLinPS Lite Translator ELT Family SPICE I/O Model Kit MC10ELT28
ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information Guide NB100LVEP91
Interfacing Between LVDS and ECL NB100ELT23L
Interfacing with ECLinPS NB100LVEP91
Metastability and the ECLinPS Family MC10EPT20
Odd Number Divide By Counters with 50% Outputs and Synchronous Clocks NUP4201
Phase Lock Loop General Operations MC10H604
Storage and Handling of Drypack Surface Mount Device NB3U23C
Termination of ECL Logic Devices NB100LVEP91
The ECL Translator Guide NB100LVEP91
Thermal Analysis and Reliability of WIRE BONDED ECL NB100LVEP91
Using Wire-OR Ties in ECLInPS™ Designs MC10H351
IBIS Model for MC100ELT28D MC100ELT28
IBIS Model for MC100ELT28DT MC100ELT28
SOIC-8 Narrow Body CM1216
TSSOP 8 3.0x3.0x0.95 mm NB100ELT23L
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