MC100EP01: ECL 4-Input OR/NOR Gate

The MC10EP01 is a 4-input OR/NOR gate. The device is functionally equivalent to the EL01 device, LVEL01, and E101 (a quad version). With AC performance much faster than the LVEL01device, the EP01 is ideal for applications requiring the fastest AC performance available. The 100 Series contains temperature compensation.

Features
  • 230ps Typical Propagation Delay
  • Maximum Frequency > 3 GHz Typical
  • PECL Mode Operating Range: VCC= 3.0 V to 5.5 V with VEE= 0 V
  • NECL Mode Operating Range: VCC= 0 V with VEE= -3.0 V to -5.5 V
  • Open Input Default State
  • Pb-Free Packages are Available
Applications
  • Hi-Speed AC Performance.
Application Notes (16)
Document TitleDocument ID/SizeRevisionRevision Date
AC Characteristics of ECL DevicesAND8090/D (896.0kB)1
Clock Generation and Clock and Data Marking and Ordering Information GuideAND8002/D (71kB)12
Designing with PECL (ECL at +5.0 V)AN1406/D (105.0kB)2
ECL Clock Distribution TechniquesAN1405/D (54.0kB)1
ECLinPS Plus™ Spice Modeling KitAND8009/D (343.0kB)11
ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information GuideAND8002 (71kB)12
Interfacing Between LVDS and ECLAN1568/D (121.0kB)11
Interfacing with ECLinPSAND8066/D (72kB)3
Metastability and the ECLinPS FamilyAN1504/D (103.0kB)3
Odd Number Divide By Counters with 50% Outputs and Synchronous ClocksAND8001/D (90.0kB)0
Phase Lock Loop General OperationsAND8040/D (64.0kB)3
Storage and Handling of Drypack Surface Mount DeviceAND8003/D (49kB)2Mar, 2016
Termination of ECL Logic DevicesAND8020/D (176.0kB)6
The ECL Translator GuideAN1672/D (142.0kB)12
Thermal Analysis and Reliability of WIRE BONDED ECLAND8072/D (119.0kB)5
Using Wire-OR Ties in ECLInPS™ DesignsAN1650/D (1130.0kB)3
Data Sheets (1)
Document TitleDocument ID/SizeRevisionRevision Date
3.3 V / 5 V ECL 4-Input OR/NORMC10EP01/D (174kB)10Aug, 2016
Simulation Models (2)
Document TitleDocument ID/SizeRevisionRevision Date
IBIS Model for MC100EP01D 3.3VMC100EP01D_33.IBS (5.0kB)1
IBIS Model for MC100EP01DT 3.3VMC100EP01DT_33.IBS (5.0kB)1
Package Drawings (3)
Document TitleDocument ID/SizeRevision
DFN8 2.0x2.0x0.9mm, 0.5p506AA (31.8kB)F
SOIC-8 Narrow Body751-07 (62.6kB)AK
TSSOP 8 3.0x3.0x0.95 mm948R-02 (77.3kB)A
Order Information
ProductStatusCompliancePackageMSL*ContainerBudgetary Price/Unit
MC100EP01DGActivePb-free Halide freeSOIC-8751-071Tube98Contact BDTIC
MC100EP01DR2GLifetimePb-free Halide freeSOIC-8751-071Tape and Reel2500
MC100EP01DTGActivePb-free Halide freeTSSOP-8948R-023Tube100Contact BDTIC
MC100EP01DTR2GLifetimePb-free Halide freeTSSOP-8948R-023Tape and Reel2500
MC100EP01MNR4GLast ShipmentsPb-free Halide freeDFN-8506AA1Tape and Reel1000
Specifications
ProductTypeChannelsInput LevelOutput LevelVCC Typ (V)fToggle Max (MHz)tpd Typ (ns)tJitter Typ (ps)tR & tF Max (ps)
MC100EP01DGOR/NOR1ECL CMLECL3.3 530000.270.2170
MC100EP01DTGOR/NOR1ECL CMLECL5 3.330000.270.2170
3.3 V / 5 V ECL 4-Input OR/NOR (174kB) MC10EP01
AC Characteristics of ECL Devices NB100LVEP91
Clock Generation and Clock and Data Marking and Ordering Information Guide NB100LVEP91
Designing with PECL (ECL at +5.0 V) NB100LVEP91
ECL Clock Distribution Techniques NB100LVEP91
ECLinPS Plus™ Spice Modeling Kit MC10EPT20
ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information Guide NB100LVEP91
Interfacing Between LVDS and ECL NB100ELT23L
Interfacing with ECLinPS NB100LVEP91
Metastability and the ECLinPS Family MC10EPT20
Odd Number Divide By Counters with 50% Outputs and Synchronous Clocks NUP4201
Phase Lock Loop General Operations MC10H604
Storage and Handling of Drypack Surface Mount Device NB3U23C
Termination of ECL Logic Devices NB100LVEP91
The ECL Translator Guide NB100LVEP91
Thermal Analysis and Reliability of WIRE BONDED ECL NB100LVEP91
Using Wire-OR Ties in ECLInPS™ Designs MC10H351
IBIS Model for MC100EP01D 3.3V MC100EP01
IBIS Model for MC100EP01DT 3.3V MC100EP01
SOIC-8 Narrow Body CM1216
TSSOP 8 3.0x3.0x0.95 mm NB100ELT23L
DFN8 2.0x2.0x0.9mm, 0.5p NUF4220