MC100EP210S: Clock Driver, 1:5 Differential, Dual LVDS, 2.5 V

The MC100EP210S is a low skew 1-to-5 dual differential driver, designed with LVDS clock distribution in mind. The LVDS or LVPECL input signals are differential and the signal is fanned out to five identical differential LVDS outputs. The EP210S specifically guarantees low output-to-output skew. Optimal design, layout, and processing minimize skew within a device and from device to device. Two internal 50-ohm resistors are provided across the inputs. For LVDS inputs, VTA and VTB pins should be unconnected. For LVPECL inputs, VTA and VTB pins should be connected to the VTT (VCC - 2.0 V) supply. Designers can take advantage of the EP210S performance to distribute low skew LVDS clocks across the backplane or the board. Special considerations are required for differential inputs under No Signal conditions to prevent instability.

Features

20 ps Typical Output-to-Output Skew
85 ps Typical Device-to-Device Skew
550 ps Typical Propagation Delay
The 100 Series contains temperature compensation.
Maximum Frequency > 1 Ghz
Operating Range: VCC = 2.375 V to 2.625 V with VEE = 0 V
Internal 50Ω Input Termination Resistors
LVDS Input/Output Compatible
Pb-Free Packages are Available

Applications

High Performance Logic for test systems and work stations. Clock fan out in routers, switches and other networking applications

Application Notes (15)

Document Title	Document ID/Size	Revision	Revision Date
AC Characteristics of ECL Devices	AND8090/D (896.0kB)	1
Clock Generation and Clock and Data Marking and Ordering Information Guide	AND8002/D (71kB)	12
Clock Management Design Using Low Skew and Low Jitter Devices	TND301/D (205.0kB)	0
Designing with PECL (ECL at +5.0 V)	AN1406/D (105.0kB)	2
ECL Clock Distribution Techniques	AN1405/D (54.0kB)	1
ECLinPS Plus™ Spice Modeling Kit	AND8009/D (343.0kB)	11
ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information Guide	AND8002 (71kB)	12
Interfacing Between LVDS and ECL	AN1568/D (121.0kB)	11
Interfacing with ECLinPS	AND8066/D (72kB)	3
Odd Number Divide By Counters with 50% Outputs and Synchronous Clocks	AND8001/D (90.0kB)	0
Phase Lock Loop General Operations	AND8040/D (64.0kB)	3
Storage and Handling of Drypack Surface Mount Device	AND8003/D (49kB)	2	Mar, 2016
Termination of ECL Logic Devices	AND8020/D (176.0kB)	6
The ECL Translator Guide	AN1672/D (142.0kB)	12
Thermal Analysis and Reliability of WIRE BONDED ECL	AND8072/D (119.0kB)	5

Data Sheets (1)

Document Title	Document ID/Size	Revision	Revision Date
2.5V 1:5 Dual Differential LVDS Clock Driver	MC100EP210S/D (138.0kB)	10

Simulation Models (2)

Document Title	Document ID/Size	Revision	Revision Date
ECLinPS Plus SPICE Modeling Kit	AND8009 (343.0kB)	11
IBIS Model for mc100ep210sfa 2.5 VCC	MC100EP210SFA_25.IBS (28.0kB)	4

Package Drawings (1)

Document Title	Document ID/Size	Revision
QFN32, 5x5, 0.5P, 3.1x3.1EP	488AM (57.4kB)	A

Order Information

Product	Status	Compliance	Package		MSL*	Container		Budgetary Price/Unit
MC100EP210SFAG	Active	Pb-free Halide free	LQFP-32	Contact BDTIC	2	Tray JEDEC	250	Contact BDTIC
MC100EP210SFAR2G	Active	Pb-free Halide free	LQFP-32	Contact BDTIC	2	Tape and Reel	2000	Contact BDTIC
MC100EP210SFATWG	Lifetime	Pb-free Halide free	LQFP-32	Contact BDTIC	2	Tape and Reel	2000
MC100EP210SMNG	Active	Pb-free Halide free	QFN-32	488AM	1	Tube	74	Contact BDTIC
MC100EP210SMNR4G	Active	Pb-free Halide free	QFN-32	488AM	1	Tape and Reel	1000	Contact BDTIC

Specifications

Product	Type	Channels	Input / Output Ratio	Input Level	Output Level	VCC Typ (V)	tJitterRMS Typ (ps)	tskew(o-o) Max (ps)	tpd Typ (ns)	tR & tF Max (ps)	fmaxClock Typ (MHz)
MC100EP210SFAG	Buffer	2	1:5	CML ECL LVDS	LVDS	2.5	0.2	25	0.55	200	1000
MC100EP210SFAR2G	Buffer	2	1:5	ECL CML LVDS	LVDS	2.5	0.2	25	0.55	200	1000
MC100EP210SMNG	Buffer	2	1:5	ECL LVDS CML	LVDS	2.5	0.2	25	0.55	200	1000
MC100EP210SMNR4G	Buffer	2	1:5	LVDS ECL CML	LVDS	2.5	0.2	25	0.55	200	1000