MC100EP33: 3.3 V / 5.0 V ECL ÷·4 Divider _ BDTIC a Leading Distributor in China

MC100EP33: 3.3 V / 5.0 V ECL ÷·4 Divider

The MC10/100EP33 is an integrated divide by 4 divider. The differential clock inputs.The VBB pin, an internally generated voltage supply, is available to this device only. For single-ended input conditions, the unused differential input is connected to VBB as a switching reference voltage.VBB may also rebias AC coupled inputs. When used, decouple VBB and VCC via a 0.01 uF capacitor and limit current sourcing or sinking to 0.5mA. When not used, VBB should be left open.The reset pin is asynchronous and is asserted on the rising edge. Upon power-up, the internal flip-flops will attain a random state; the reset allows for the synchronization of multiple EP33's in a system.The 100 Series contains temperature compensation.

Features

320ps Propagation Delay
Maximum Frequency > 4 GHz Typical
PECL Mode Operating Range: VCC= 3.0 V to 5.5 V with VEE= 0 V
NECL Mode Operating Range: VCC= 0 V with VEE= -3.0 V to -5.5 V
Open Input Default State
Safety Clamp on Inputs
Q Output will default LOW with inputs open or at VEE
VBB Output
Pb-Free Packages are Available

Applications

Phase Lock Loops

Application Notes (17)

Document Title	Document ID/Size	Revision	Revision Date
AC Characteristics of ECL Devices	AND8090/D (896.0kB)	1
Board Mounting Notes for Quad Flat-Pack No-Lead Package (QFN)	AND8086/D (40.0kB)	0
Clock Generation and Clock and Data Marking and Ordering Information Guide	AND8002/D (71kB)	12
Designing with PECL (ECL at +5.0 V)	AN1406/D (105.0kB)	2
ECL Clock Distribution Techniques	AN1405/D (54.0kB)	1
ECLinPS Plus™ Spice Modeling Kit	AND8009/D (343.0kB)	11
ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information Guide	AND8002 (71kB)	12
Interfacing Between LVDS and ECL	AN1568/D (121.0kB)	11
Interfacing with ECLinPS	AND8066/D (72kB)	3
Metastability and the ECLinPS Family	AN1504/D (103.0kB)	3
Odd Number Divide By Counters with 50% Outputs and Synchronous Clocks	AND8001/D (90.0kB)	0
Phase Lock Loop General Operations	AND8040/D (64.0kB)	3
Storage and Handling of Drypack Surface Mount Device	AND8003/D (49kB)	2	Mar, 2016
Termination of ECL Logic Devices	AND8020/D (176.0kB)	6
The ECL Translator Guide	AN1672/D (142.0kB)	12
Thermal Analysis and Reliability of WIRE BONDED ECL	AND8072/D (119.0kB)	5
Using Wire-OR Ties in ECLInPS™ Designs	AN1650/D (1130.0kB)	3

Data Sheets (1)

Document Title	Document ID/Size	Revision	Revision Date
3.3 V / 5 V ECL Divide by 4 Divider	MC10EP33/D (186kB)	11	Aug, 2016

Simulation Models (3)

Document Title	Document ID/Size	Revision
IBIS Model for MC100EP33D 3.3V	MC100EP33D_33.IBS (5.0kB)	3
IBIS Model for MC100EP33DT 3.3V	MC100EP33DT_33.IBS (5.0kB)	2
IBIS Model for mc100ep33dt -5.0V	MC100EP33DT_-50.IBS (5.0kB)	1

Package Drawings (3)

Document Title	Document ID/Size	Revision
DFN8 2.0x2.0x0.9mm, 0.5p	506AA (31.8kB)	F
SOIC-8 Narrow Body	751-07 (62.6kB)	AK
TSSOP 8 3.0x3.0x0.95 mm	948R-02 (77.3kB)	A

Order Information

Product	Status	Compliance	Package		MSL*	Container		Budgetary Price/Unit
MC100EP33DG	Active	Pb-free Halide free	SOIC-8	751-07	1	Tube	98	Contact BDTIC
MC100EP33DR2G	Lifetime	Pb-free Halide free	SOIC-8	751-07	1	Tape and Reel	2500
MC100EP33DTG	Active	Pb-free Halide free	TSSOP-8	948R-02	3	Tube	100	Contact BDTIC
MC100EP33DTR2G	Active	Pb-free Halide free	TSSOP-8	948R-02	3	Tape and Reel	2500	Contact BDTIC
MC100EP33MNR4G	Active	Pb-free Halide free	DFN-8	506AA	1	Tape and Reel	1000	Contact BDTIC

Specifications

Product	Type	Input Level	Output Level	VCC Typ (V)	fMax Typ (MHz)	tpd Typ (ns)	tR & tF Max (ps)
MC100EP33DG	Divider	ECL CML	ECL	3.3 5	4000	0.38	200
MC100EP33DTG	Divider	ECL CML	ECL	5 3.3	4000	0.38	200
MC100EP33DTR2G	Divider	CML ECL	ECL	5 3.3	4000	0.38	200
MC100EP33MNR4G	Divider	ECL CML	ECL	3.3 5	4000	0.38	200