MC100EP56: Multiplexer, 2:1 Differential, Dual ECL, 3.3 V / 5.0 V

The MC10/100EP56 is a dual, fully differential 2:1 multiplexer. The differential data path makes the device ideal for multiplexing low skew clock or other skew sensitive signals. Multiple VBB pins are provided.The VBB pin, an internally generated voltage supply, is available to this device only. For single-ended input conditions, the unused differential input is connected to VBB as a switching reference voltage. VBB may also rebias AC coupled inputs. When used, decouple VBB and VCC via a 0.01uF capacitor and limit current sourcing or sinking to 0.5mA. When not used, VBB should be left open.The device features both individual and common select inputs to address both data path and random logic applications.The 100 Series contains temperature compensation.

Features

360ps Typical Propagation Delays
Maximum Frequency > 3 GHz Typical
PECL Mode Operating Range: VCC = 3.0 V to 5.5 V with VEE = 0 V
NECL Mode Operating Range: VCC = 0 V with VEE = -3.0 V to -5.5 V
Open Input Default State
Safety Clamp on Inputs
Separate and Common Select
Q Output will default LOW with inputs open or at VEE
VBB Outputs
Pb-Free Packages are Available

Applications

Ideal for multiplexing low skew clock or other skew sensitive signals

Application Notes (16)

Document Title	Document ID/Size	Revision	Revision Date
AC Characteristics of ECL Devices	AND8090/D (896.0kB)	1
Clock Generation and Clock and Data Marking and Ordering Information Guide	AND8002/D (71kB)	12
Designing with PECL (ECL at +5.0 V)	AN1406/D (105.0kB)	2
ECL Clock Distribution Techniques	AN1405/D (54.0kB)	1
ECLinPS Plus™ Spice Modeling Kit	AND8009/D (343.0kB)	11
ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information Guide	AND8002 (71kB)	12
Interfacing Between LVDS and ECL	AN1568/D (121.0kB)	11
Interfacing with ECLinPS	AND8066/D (72kB)	3
Metastability and the ECLinPS Family	AN1504/D (103.0kB)	3
Odd Number Divide By Counters with 50% Outputs and Synchronous Clocks	AND8001/D (90.0kB)	0
Phase Lock Loop General Operations	AND8040/D (64.0kB)	3
Storage and Handling of Drypack Surface Mount Device	AND8003/D (49kB)	2	Mar, 2016
Termination of ECL Logic Devices	AND8020/D (176.0kB)	6
The ECL Translator Guide	AN1672/D (142.0kB)	12
Thermal Analysis and Reliability of WIRE BONDED ECL	AND8072/D (119.0kB)	5
Using Wire-OR Ties in ECLInPS™ Designs	AN1650/D (1130.0kB)	3

Data Sheets (1)

Document Title	Document ID/Size	Revision	Revision Date
3.3V / 5V ECL Dual Differential 2:1 Multiplexer	MC10EP56/D (121kB)	17

Simulation Models (3)

Document Title	Document ID/Size	Revision
IBIS Model for MC100EP56DT -3.3V	MC100EP56DT_-33.IBS (11.0kB)	3
IBIS Model for MC100EP56DT 3.3V	MC100EP56DT_33.IBS (11.0kB)	4
IBIS Model for MC100EP56DW 3.3V	MC100EP56DW_33.IBS (11.0kB)	3

Package Drawings (3)

Document Title	Document ID/Size	Revision
QFN20, 4x4, 0.5P	485E-01 (60.9kB)	B
SOIC-20 WB	751D-05 (36.3kB)	H
TSSOP-20 WB	948E-02 (39.7kB)	D

Order Information

Product	Status	Compliance	Package		MSL*	Container		Budgetary Price/Unit
MC100EP56DTG	Active	Pb-free Halide free	TSSOP-20	948E-02	1	Tube	75	Contact BDTIC
MC100EP56DTR2G	Active	Pb-free Halide free	TSSOP-20	948E-02	1	Tape and Reel	2500	Contact BDTIC
MC100EP56DWG	Active	Pb-free Halide free	SOIC-20W	751D-05	3	Tube	38	Contact BDTIC
MC100EP56DWR2G	Active	Pb-free Halide free	SOIC-20W	751D-05	3	Tape and Reel	1000	Contact BDTIC
MC100EP56MNG	Active	Pb-free Halide free	QFN-20	485E-01	1	Tube	92	Contact BDTIC
MC100EP56MNTXG	Last Shipments	Pb-free Halide free	QFN-20	485E-01	1	Tape and Reel	3000

Specifications

Product	Input/Output Ratio	Channels	Input Level	Output Level	VCC Typ (V)	fMax Typ (MHz)	tJitter Typ (ps)	tskew(OO) Max (ps)	tpd Typ (ns)
MC100EP56DTG	2:1	2	CML ECL	ECL	3.3 5	3000	0.2	100	0.36
MC100EP56DTR2G	2:1	2	ECL CML	ECL	3.3 5	3000	0.2	100	0.36
MC100EP56DWG	2:1	2	CML ECL	ECL	3.3 5	3000	0.2	100	0.36
MC100EP56DWR2G	2:1	2	ECL CML	ECL	3.3 5	3000	0.2	100	0.36
MC100EP56MNG	2:1	2	ECL CML	ECL	3.3 5	3000	0.2	100	0.36