MC100EP809: Clock Driver, 2:1:9 Differential HSTL / PECL to HSTL, 3.3 V

The MC100EP809 is a low skew 2:1:9 differential bus clock driver, designed with clock distribution in mind, accepting two clock sources into an input multiplexer. The part is designed for use in low voltage applications which require a large number of outputs to drive precisely aligned low skew signals to their destination. The two clock inputs are one differential HSTL and one differential LVPECL. Both input pairs can accept LVDS levels. They are selected by the CLK_SEL pin which is LVTTL. To avoid generation of a runt clock pulse when the device is enabled/disabled, the Output Enable (OE), which is LVTTL, is synchronous so that the outputs will only be enabled/disabled when they are already in LOW state.The MC100EP809 guarantees low output-to-output skew. The optimal design, layout, and processing minimize skew within a device and from lot to lot. The MC100EP809 output structure uses open emitter architecture and will be terminated with 50 to ground instead of a standard HSTL configuration. To ensure that tight skew specification is realized, both sides of the differential output need to be terminated identically into 50 even if only one output is being used. If an output pair is unused, both outputs may be left open (unterminated) without affecting skew.Designers can take advantage of the EP809's performance to distribute low skew clocks across the backplane of the board. HSTL clock inputs may be driven single-end by biasing the non-driven pin in an input pair.

Features
  • 100 ps Typical Device-to-Device Skew
  • 15 ps Typical Within Device Skew
  • HSTL Compatible Outputs Drive 50Ω to Ground with no Offset Voltage
  • Maximum Frequency > 750 MHz
  • 850 ps Typical Propagation Delay
  • Fully Compatible with Micrel SY89809L
  • PECL and HSTL Mode Operating Range: VCCI = 3 V to 3.6 V with GND = 0 V, VCCO = 1.6 V to 2.0 V
  • Open Input Default State
  • Pb-Free Packages are Available
Applications
  • Clock distribution
Application Notes (13)
Document TitleDocument ID/SizeRevisionRevision Date
AC Characteristics of ECL DevicesAND8090/D (896.0kB)1
Clock Generation and Clock and Data Marking and Ordering Information GuideAND8002/D (71kB)12
Designing with PECL (ECL at +5.0 V)AN1406/D (105.0kB)2
ECL Clock Distribution TechniquesAN1405/D (54.0kB)1
ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information GuideAND8002 (71kB)12
Interfacing Between LVDS and ECLAN1568/D (121.0kB)11
Interfacing with ECLinPSAND8066/D (72kB)3
Odd Number Divide By Counters with 50% Outputs and Synchronous ClocksAND8001/D (90.0kB)0
Phase Lock Loop General OperationsAND8040/D (64.0kB)3
Storage and Handling of Drypack Surface Mount DeviceAND8003/D (49kB)2Mar, 2016
Termination of ECL Logic DevicesAND8020/D (176.0kB)6
The ECL Translator GuideAN1672/D (142.0kB)12
Thermal Analysis and Reliability of WIRE BONDED ECLAND8072/D (119.0kB)5
Data Sheets (1)
Document TitleDocument ID/SizeRevisionRevision Date
3.3V 2:1:9 Differential HSTL/PECL to HSTL Clock Driver with LVTTL Clock Select and EnableMC100EP809/D (106kB)10
Simulation Models (1)
Document TitleDocument ID/SizeRevisionRevision Date
IBIS Model for mc100ep809faMC100EP809FA.IBS (25.0kB)3
Package Drawings (1)
Document TitleDocument ID/SizeRevision
QFN32, 5x5, 0.5P, 3.1x3.1EP488AM (57.4kB)A
Order Information
ProductStatusCompliancePackageMSL*ContainerBudgetary Price/Unit
MC100EP809FAGActivePb-free Halide freeLQFP-32Contact BDTIC2Tray JEDEC250Contact BDTIC
MC100EP809FAR2GActivePb-free Halide freeLQFP-32Contact BDTIC2Tape and Reel2000Contact BDTIC
MC100EP809MNGActivePb-free Halide freeQFN-32488AM1Tube74Contact BDTIC
MC100EP809MNR4GActivePb-free Halide freeQFN-32488AM1Tape and Reel1000Contact BDTIC
Specifications
ProductTypeChannelsInput / Output RatioInput LevelOutput LevelVCC Typ (V)tJitterRMS Typ (ps)tskew(o-o) Max (ps)tpd Typ (ns)tR & tF Max (ps)fmaxClock Typ (MHz)fmaxData Typ (Mbps)
MC100EP809FAGBuffer12:1:9ECL CML HSTL LVDSHSTL3.31.4500.85 0.82600750
MC100EP809FAR2GBuffer12:1:9HSTL CML LVDS ECLHSTL3.31.4500.82 0.85600750
MC100EP809MNGBuffer12:1:9CML LVDS HSTL ECLHSTL3.31.4500.85 0.82600750
MC100EP809MNR4GBuffer12:1:9ECL HSTL CML LVDSHSTL3.31.4500.82 0.85600750
3.3V 2:1:9 Differential HSTL/PECL to HSTL Clock Driver with LVTTL Clock Select and Enable (106kB) MC100EP809
AC Characteristics of ECL Devices NB100LVEP91
Clock Generation and Clock and Data Marking and Ordering Information Guide NB100LVEP91
Designing with PECL (ECL at +5.0 V) NB100LVEP91
ECL Clock Distribution Techniques NB100LVEP91
ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information Guide NB100LVEP91
Interfacing Between LVDS and ECL NB100ELT23L
Interfacing with ECLinPS NB100LVEP91
Odd Number Divide By Counters with 50% Outputs and Synchronous Clocks NUP4201
Phase Lock Loop General Operations MC10H604
Storage and Handling of Drypack Surface Mount Device NB3U23C
Termination of ECL Logic Devices NB100LVEP91
The ECL Translator Guide NB100LVEP91
Thermal Analysis and Reliability of WIRE BONDED ECL NB100LVEP91
IBIS Model for mc100ep809fa MC100EP809
QFN32, 5x5, 0.5P, 3.1x3.1EP NCN6804