MC100EPT20: Translator, LVTTL / LVCMOS to Differential LVPECL
The MC10EPT20 is a 3.3 V TTL/CMOS to differential PECL translator. Because PECL (Positive ECL) levels are used, only +3.3 V and ground are required. The small outline SOIC-8 package and the single gate of the EPT20 makes it ideal for those applications where space, performance, and low power are at a premium.
Features- 390ps Typical Propagation Delay
- Maximum Frequency > 1 Ghz Typical
- PNP TTL Inputs for Minimal Loading
- Operating Range V CC = 3.0V to 3.6V with GND = 0
- Q Output will default HIGH with inputs open
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Applications- Precision Clock Translation
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Application Notes (18)
Data Sheets (1)
Simulation Models (1)
Package Drawings (3)
Order Information
| Product | Status | Compliance | Package | MSL* | Container | Budgetary Price/Unit |
|---|
| MC100EPT20DG | Active | Pb-free
Halide free | SOIC-8 | 751-07 | 1 | Tube | 98 | Contact BDTIC |
| MC100EPT20DR2G | Active | Pb-free
Halide free | SOIC-8 | 751-07 | 1 | Tape and Reel | 2500 | Contact BDTIC |
| MC100EPT20DTG | Active | Pb-free
Halide free | TSSOP-8 | 948R-02 | 3 | Tube | 100 | Contact BDTIC |
| MC100EPT20DTR2G | Active | Pb-free
Halide free | TSSOP-8 | 948R-02 | 3 | Tape and Reel | 2500 | Contact BDTIC |
| MC100EPT20MNR4G | Active | Pb-free
Halide free | DFN-8 | 506AA | 1 | Tape and Reel | 1000 | Contact BDTIC |
Specifications
| Product | Channels | Input Level | Output Level | VCC Typ (V) | fMax Typ (MHz) | tpd Typ (ns) | tR & tF Max (ps) |
|---|
| MC100EPT20DG | 1 | TTL
CMOS | ECL | 3.3 | 1000 | 0.37 | 170 |
| MC100EPT20DR2G | 1 | TTL
CMOS | ECL | 3.3 | 1000 | 0.37 | 170 |
| MC100EPT20DTG | 1 | TTL
CMOS | ECL | 3.3 | 1000 | 0.37 | 170 |
| MC100EPT20DTR2G | 1 | TTL
CMOS | ECL | 3.3 | 1000 | 0.37 | 170 |
| MC100EPT20MNR4G | 1 | CMOS
TTL | ECL | 3.3 | 1000 | 0.37 | 170 |
