MC100EPT23: Translator, Dual Differential LVPECL to LVTTL

The MC100EPT23 is a dual differential LVPECL/LVDS/CML to LVTTL/LVCMOS translator. Because LVPECL/LVDS/CML input levels and LVTTL/LVCMOS output levels are used only +3.3V and ground are required. The small outline 8-lead SOIC package and the dual gate design of the EPT23 makes it ideal for applications which require the translation of a clock and a data signal.The EPT23 is available in only the ECL 100K standard. Since there are no LVPECL outputs or an external VBB reference, the EPT23 does not require both ECL standard versions. The LVPECL inputs are differential. Therefore, the MC100EPT23 can accept any standard differential LVPECL input referenced from a VCC of +3.3V.

Features

1.5ns Typical Propagation Delay
Maximum Operating Frequency > 275MHz
24mA LVTTL Outputs
Operating Range: VCC= 3.0 V to 3.6 V with GND = 0 V
Open Input Default State
Q Output will default LOW with inputs open or at GND
Pb-Free Packages are Available

Application Notes (18)

Document Title	Document ID/Size	Revision	Revision Date
AC Characteristics of ECL Devices	AND8090/D (896.0kB)	1
Board Mounting Notes for Quad Flat-Pack No-Lead Package (QFN)	AND8086/D (40.0kB)	0
Clock Generation and Clock and Data Marking and Ordering Information Guide	AND8002/D (71kB)	12
Clock Management Design Using Low Skew and Low Jitter Devices	TND301/D (205.0kB)	0
Designing with PECL (ECL at +5.0 V)	AN1406/D (105.0kB)	2
ECL Clock Distribution Techniques	AN1405/D (54.0kB)	1
ECLinPS Plus™ Spice Modeling Kit	AND8009/D (343.0kB)	11
ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information Guide	AND8002 (71kB)	12
EPT Spice Modeling Kit	AND8014/D (63.0kB)	0
Interfacing Between LVDS and ECL	AN1568/D (121.0kB)	11
Interfacing with ECLinPS	AND8066/D (72kB)	3
Metastability and the ECLinPS Family	AN1504/D (103.0kB)	3
Odd Number Divide By Counters with 50% Outputs and Synchronous Clocks	AND8001/D (90.0kB)	0
Phase Lock Loop General Operations	AND8040/D (64.0kB)	3
Storage and Handling of Drypack Surface Mount Device	AND8003/D (49kB)	2	Mar, 2016
Termination of ECL Logic Devices	AND8020/D (176.0kB)	6
The ECL Translator Guide	AN1672/D (142.0kB)	12
Thermal Analysis and Reliability of WIRE BONDED ECL	AND8072/D (119.0kB)	5

Data Sheets (1)

Document Title	Document ID/Size	Revision	Revision Date
3.3 V Dual Differential LVPECL/LVDS/CML to LVTTL/LVCMOS Translator	MC100EPT23/D (157kB)	19	Aug, 2016

Simulation Models (4)

Document Title	Document ID/Size	Revision
EPT21/23/25 ECLinPS PlusE Translator TTL output SPICE Modeling Kit	AND8118/D (53.0kB)	0
IBIS Model for mc100ept23mn 3.3 V	MC100EPT23MN_33.IBS (7.0kB)	1
IBS Model for MC100EPT23D 3.3V	MC100EPT23D_33.IBS (7.0kB)	3
IBS Model for MC100EPT23DT	MC100EPT23DT_33.IBS (7.0kB)	3

Package Drawings (3)

Document Title	Document ID/Size	Revision
DFN8 2.0x2.0x0.9mm, 0.5p	506AA (31.8kB)	F
SOIC-8 Narrow Body	751-07 (62.6kB)	AK
TSSOP 8 3.0x3.0x0.95 mm	948R-02 (77.3kB)	A

Order Information

Product	Status	Compliance	Package		MSL*	Container		Budgetary Price/Unit
MC100EPT23DG	Active	Pb-free Halide free	SOIC-8	751-07	1	Tube	98	Contact BDTIC
MC100EPT23DR2G	Active	Pb-free Halide free	SOIC-8	751-07	1	Tape and Reel	2500	Contact BDTIC
MC100EPT23DTG	Active	Pb-free Halide free	TSSOP-8	948R-02	3	Tube	100	Contact BDTIC
MC100EPT23DTR2G	Active	Pb-free Halide free	TSSOP-8	948R-02	3	Tape and Reel	2500	Contact BDTIC
MC100EPT23MNR4G	Active	Pb-free Halide free	DFN-8	506AA	1	Tape and Reel	1000	Contact BDTIC

Specifications

Product	Channels	Input Level	Output Level	VCC Typ (V)	fMax Typ (MHz)	tpd Typ (ns)	tR & tF Max (ps)
MC100EPT23DG	2	ECL LVDS CML	TTL	3.3	350	1.5	900
MC100EPT23DR2G	2	CML LVDS ECL	TTL	3.3	350	1.5	900
MC100EPT23DTG	2	CML ECL LVDS	TTL	3.3	350	1.5	900
MC100EPT23DTR2G	2	LVDS ECL CML	TTL	3.3	350	1.5	900
MC100EPT23MNR4G	2	CML ECL LVDS	TTL	3.3	350	1.5	900