MC100LVEL91: Translator, Triple LVPECL / PECL Input to ECL Output

The MC100LVEL91 is a triple LVPECL input to ECL output translator. The device receives standard or low voltage differential PECL signals, determined by the VCC supply level, and translates them to differential -3.3 V to -5.0 V ECL output signals. (For translation from 5.0 V PECL to -5 V ECL output, see MC100EL91.)To accomplish the level translation the LVEL91 requires three power rails. The VCC supply should be connected to the positive supply, and the VEE pin should be connected to the negative power supply. The GND pins are connected to the system ground plane. Both VEE and VCC should be bypassed to ground via 0.01 µF capacitors. Under open input conditions, the Dbar input will be biased at VCC/2 and the D input will be pulled to GND. This condition will force the Q output to a low, ensuring stability.The VBB pin, an internally generated voltage supply, is available to this device only. For single-ended input conditions, the unused differential input is connected to VBB as a switching reference voltage. VBB may also rebias AC coupled inputs. When used, decouple VBB and VCC via a 0.01 µF capacitor and limit current sourcing or sinking to 0.5 mA. When not used, VBB should be left open.

Features
  • 620 ps Typical Propagation Delay
  • The 100 Series Contains Temperature Compensation
  • Operating Range: VCC = 3.8 V to 3.3 V; VEE = -3.0 V to -3.8 V; GND= 0 V
  • Q Output will Default LOW with Inputs Open or at GND
  • Pb-Free Packages are Available
Application Notes (15)
Document TitleDocument ID/SizeRevisionRevision Date
AC Characteristics of ECL DevicesAND8090/D (896.0kB)1
Clock Generation and Clock and Data Marking and Ordering Information GuideAND8002/D (71kB)12
Clock Management Design Using Low Skew and Low Jitter DevicesTND301/D (205.0kB)0
Designing with PECL (ECL at +5.0 V)AN1406/D (105.0kB)2
ECL Clock Distribution TechniquesAN1405/D (54.0kB)1
ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information GuideAND8002 (71kB)12
Interfacing Between LVDS and ECLAN1568/D (121.0kB)11
Interfacing with ECLinPSAND8066/D (72kB)3
Odd Number Divide By Counters with 50% Outputs and Synchronous ClocksAND8001/D (90.0kB)0
Phase Lock Loop General OperationsAND8040/D (64.0kB)3
Storage and Handling of Drypack Surface Mount DeviceAND8003/D (49kB)2Mar, 2016
Termination of ECL Logic DevicesAND8020/D (176.0kB)6
The ECL Translator GuideAN1672/D (142.0kB)12
Thermal Analysis and Reliability of WIRE BONDED ECLAND8072/D (119.0kB)5
Using Wire-OR Ties in ECLInPS™ DesignsAN1650/D (1130.0kB)3
Data Sheets (1)
Document TitleDocument ID/SizeRevisionRevision Date
3.3 V Triple LVPECL Input to -3.3 V to -5.0 V ECL Output TranslatorMC100LVEL91/D (141kB)12Jul, 2016
Simulation Models (2)
Document TitleDocument ID/SizeRevisionRevision Date
IBIS Model for mc100lvel91dw 3.3VCC -3.3VEEMC100LVEL91DW_33_-33.IBS (6.0kB)2
Low Voltage ECLinPS SPICE Modeling KitAN1560/D (88.0kB)5
Package Drawings (1)
Document TitleDocument ID/SizeRevision
SOIC-20 WB751D-05 (36.3kB)H
Order Information
ProductStatusCompliancePackageMSL*ContainerBudgetary Price/Unit
MC100LVEL91DWGActivePb-free Halide freeSOIC-20W751D-053Tube38Contact BDTIC
MC100LVEL91DWR2GActivePb-free Halide freeSOIC-20W751D-053Tape and Reel1000Contact BDTIC
Specifications
ProductChannelsInput LevelOutput LevelVCC Typ (V)fMax Typ (MHz)tpd Typ (ns)tR & tF Max (ps)
MC100LVEL91DWG3ECLECL3.3 56000.62580
MC100LVEL91DWR2G3ECLECL3.3 56000.62580
3.3 V Triple LVPECL Input to -3.3 V to -5.0 V ECL Output Translator (141kB) MC100LVEL91
AC Characteristics of ECL Devices NB100LVEP91
Clock Generation and Clock and Data Marking and Ordering Information Guide NB100LVEP91
Clock Management Design Using Low Skew and Low Jitter Devices MC10H604
Designing with PECL (ECL at +5.0 V) NB100LVEP91
ECL Clock Distribution Techniques NB100LVEP91
ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information Guide NB100LVEP91
Interfacing Between LVDS and ECL NB100ELT23L
Interfacing with ECLinPS NB100LVEP91
Odd Number Divide By Counters with 50% Outputs and Synchronous Clocks NUP4201
Phase Lock Loop General Operations MC10H604
Storage and Handling of Drypack Surface Mount Device NB3U23C
Termination of ECL Logic Devices NB100LVEP91
The ECL Translator Guide NB100LVEP91
Thermal Analysis and Reliability of WIRE BONDED ECL NB100LVEP91
Using Wire-OR Ties in ECLInPS™ Designs MC10H351
IBIS Model for mc100lvel91dw 3.3VCC -3.3VEE MC100LVEL91
Low Voltage ECLinPS SPICE Modeling Kit MC100LVELT23
SOIC-20 WB NLSX3018