MC100LVELT23: Translator, Dual Differential LVPECL to LVTTL

The MC100LVELT23 is a dual differential LVPECL to LVTTL translator. Because LVPECL (Positive ECL) levels are used only +3.3V and ground are required. The small outline 8-lead SOIC package and the dual gate design of the LVELT23 makes it ideal for applications which require the translation of a clock and a data signal. The LVELT23 is available in only the ECL 100K standard. Since there are no LVPECL outputs or an external VBB reference, the LVELT23 does not require both ECL standard versions. The LVPECL inputs are differential; there is no specified difference between the differential input 10H and 100K standards. Therefore, the MC100LVELT23 can accept any standard differential LVPECL input referenced from a VCC of 3.3V.

Features
  • 2.0ns Typical Propagation Delay
  • Maximum Frequency > 180 MHz
  • Differential LVPECL Inputs
  • PECL Mode Operating Range: VCC= 3.0 V to 3.8 V with GND= 0 V
  • 24 mA LVTTL Outputs
  • Flow Through Pinouts
  • Internal Pulldown Resistors
  • Q Output will default LOW with inputs open or at GND
  • ESD Protection: >1.5 KV HBM, >100 V MM
  • Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
  • Moisture Sensitivity Level 1For Additional Information, see Application Note AND8003/D
  • Flammability Rating: UL-94 code V-0 @ 1/8", Oxygen Index 28 to 34
  • Transistor Count = 91 devices
  • Pb-Free Packages are Available
Application Notes (14)
Document TitleDocument ID/SizeRevisionRevision Date
AC Characteristics of ECL DevicesAND8090/D (896.0kB)1
Clock Generation and Clock and Data Marking and Ordering Information GuideAND8002/D (71kB)12
Clock Management Design Using Low Skew and Low Jitter DevicesTND301/D (205.0kB)0
Designing with PECL (ECL at +5.0 V)AN1406/D (105.0kB)2
ECL Clock Distribution TechniquesAN1405/D (54.0kB)1
ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information GuideAND8002 (71kB)12
Interfacing Between LVDS and ECLAN1568/D (121.0kB)11
Interfacing with ECLinPSAND8066/D (72kB)3
Odd Number Divide By Counters with 50% Outputs and Synchronous ClocksAND8001/D (90.0kB)0
Phase Lock Loop General OperationsAND8040/D (64.0kB)3
Storage and Handling of Drypack Surface Mount DeviceAND8003/D (49kB)2Mar, 2016
Termination of ECL Logic DevicesAND8020/D (176.0kB)6
The ECL Translator GuideAN1672/D (142.0kB)12
Thermal Analysis and Reliability of WIRE BONDED ECLAND8072/D (119.0kB)5
Data Sheets (1)
Document TitleDocument ID/SizeRevisionRevision Date
3.3 V Dual Differential LVPECL/LVDS to LVTTL TranslatorMC100LVELT23/D (156kB)19Jul, 2016
Simulation Models (3)
Document TitleDocument ID/SizeRevisionRevision Date
IBIS Model for MC100LVELT23DT 3.3VMC100LVELT23DT_33.IBS (7.0kB)2
IBIS Model for MC100LVELT23DT 3.3VMC100LVELT23D_33.IBS (7.0kB)5
Low Voltage ECLinPS SPICE Modeling KitAN1560/D (88.0kB)5
Package Drawings (3)
Document TitleDocument ID/SizeRevision
DFN8 2.0x2.0x0.9mm, 0.5p506AA (31.8kB)F
SOIC-8 Narrow Body751-07 (62.6kB)AK
TSSOP 8 3.0x3.0x0.95 mm948R-02 (77.3kB)A
Order Information
ProductStatusCompliancePackageMSL*ContainerBudgetary Price/Unit
MC100LVELT23DGActivePb-free Halide freeSOIC-8751-071Tube98Contact BDTIC
MC100LVELT23DR2GActivePb-free Halide freeSOIC-8751-071Tape and Reel2500Contact BDTIC
MC100LVELT23DTGActivePb-free Halide freeTSSOP-8948R-023Tube100Contact BDTIC
MC100LVELT23DTRGActivePb-free Halide freeTSSOP-8948R-023Tape and Reel2500Contact BDTIC
MC100LVELT23MNRGActivePb-free Halide freeDFN-8506AA1Tape and Reel1000Contact BDTIC
Specifications
ProductChannelsInput LevelOutput LevelVCC Typ (V)fMax Typ (MHz)tpd Typ (ns)tR & tF Max (ps)
MC100LVELT23DG2ECLTTL3.31801.7900
MC100LVELT23DR2G2ECLTTL3.31801.7900
MC100LVELT23DTG2ECLTTL3.31801.7900
MC100LVELT23DTRG2ECLTTL3.31801.7900
MC100LVELT23MNRG2ECLTTL3.31801.7900
3.3 V Dual Differential LVPECL/LVDS to LVTTL Translator (156kB) MC100LVELT23
AC Characteristics of ECL Devices NB100LVEP91
Clock Generation and Clock and Data Marking and Ordering Information Guide NB100LVEP91
Clock Management Design Using Low Skew and Low Jitter Devices MC10H604
Designing with PECL (ECL at +5.0 V) NB100LVEP91
ECL Clock Distribution Techniques NB100LVEP91
ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information Guide NB100LVEP91
Interfacing Between LVDS and ECL NB100ELT23L
Interfacing with ECLinPS NB100LVEP91
Odd Number Divide By Counters with 50% Outputs and Synchronous Clocks NUP4201
Phase Lock Loop General Operations MC10H604
Storage and Handling of Drypack Surface Mount Device NB3U23C
Termination of ECL Logic Devices NB100LVEP91
The ECL Translator Guide NB100LVEP91
Thermal Analysis and Reliability of WIRE BONDED ECL NB100LVEP91
IBIS Model for MC100LVELT23DT 3.3V MC100LVELT23
IBIS Model for MC100LVELT23DT 3.3V MC100LVELT23
Low Voltage ECLinPS SPICE Modeling Kit MC100LVELT23
SOIC-8 Narrow Body CM1216
TSSOP 8 3.0x3.0x0.95 mm NB100ELT23L
DFN8 2.0x2.0x0.9mm, 0.5p NUF4220