MC10E156: ECL 3-Bit 4:1 Mux-Latch
The MC10E/100E156 contains three 4:1 multiplexers followed by transparent latches with differential outputs. When both Latch Enables (LEN1, LEN2) are LOW, the latch is transparent, and output date is controlled by the multiplexer select controls (SEL0, SEL1). A logic HIGH on either LEN1 or LEN2 (or both) latches the outputs. The Master Reset (MR) overrides all other controls to set the Q outputs LOW.The 100 Series contains temperature compensation.
Features- 950ps Max. D to Output
- 850ps Max. LEN to Output
- Differential Outputs
- Asynchronous Master Reset
- Dual Latch-Enables
- PECL Mode Operating Range: VCC = 4.2 V to 5.7 V with VEE = 0 V
- NECL Mode Operating Range: VCC = 0 V with VEE = -4.2 V to -5.7 V
- Internal Input Pulldown Resistors
- ESD Protection: > 2 kV HBM, > 200 V MM
- Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
- Moisture Sensitivity Level 1For Additional Information, see Application Note AND8003/D
- Flammability Rating: UL-94 code V-0 @ 1/8", Oxygen Index 28 to 34
- Transistor Count = 271 devices
- Pb-Free Packages are Available
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Application Notes (17)
Data Sheets (1)
Simulation Models (1)
Package Drawings (1)
| Document Title | Document ID/Size | Revision |
|---|
| 28 LEAD PLCC | 776-02 (67.7kB) | F |
Order Information
| Product | Status | Compliance | Package | MSL* | Container | Budgetary Price/Unit |
|---|
| MC10E156FNG | Active | Pb-free
Halide free | PLCC-28 | 776-02 | 3 | Tube | 37 | Contact BDTIC |
Specifications
| Product | Input/Output Ratio | Channels | Input Level | Output Level | VCC Typ (V) | fMax Typ (MHz) | tJitter Typ (ps) | tskew(OO) Max (ps) | tpd Typ (ns) |
|---|
| MC10E156FNG | 4:1 | 3 | ECL | ECL | 5 | 1100 | 1 | 50 | 0.6 |
