MC10EL05: 5.0 V ECL 2-Input Differential AND/NAND Gate

The MC10EL/100EL05 is a 2-input differential AND/NAND gate. The device is functionally equivalent to the E404 device with higher performance capabilities. With propagation delays and output transition times significantly faster than the E404 the EL05 is ideally suited for those applications which require the ultimate in AC performance. Because a negative 2-input NAND is equivalent to a 2-input OR function, the differential inputs and outputs of the device allows the EL05 to also be used as a 2-input differential OR/NOR gate. The differential inputs employ clamp circuitry so that under open input conditions (pulled down to VEE) the input to the AND gate will be HIGH. In this way, if one set of inputs is open, the gate will remain active to the other input.The 100 Series contains temperature compensation.

Features
  • 275ps Propagation Delay
  • ESD Protection: > 1 kV HBM, > 100 V MM
  • PECL Mode Operating Range: VCC= 4.2 V to 5.7 V with VEE= 0 V
  • NECL Mode Operating Range: VCC= 0 V with VEE= -4.2 V to -5.7 V
  • Internal Input Pulldown Resistors
  • Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
  • Moisture Sensitivity Level 1For Additional Information, see Application Note AND8003/D
  • Flammability Rating: UL-94 code V-0 @ 1/8", Oxygen Index 28 to 34
  • Transistor Count = 44 devices
  • Pb-Free Packages are Available
Application Notes (17)
Document TitleDocument ID/SizeRevisionRevision Date
AC Characteristics of ECL DevicesAND8090/D (896.0kB)1
Clock Generation and Clock and Data Marking and Ordering Information GuideAND8002/D (71kB)12
Clock Management Design Using Low Skew and Low Jitter DevicesTND301/D (205.0kB)0
Designing with PECL (ECL at +5.0 V)AN1406/D (105.0kB)2
ECL Clock Distribution TechniquesAN1405/D (54.0kB)1
ECLinPS and ECLinPS Lite SPICE I/O Modeling KitAN1503/D (120.0kB)6
ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information GuideAND8002 (71kB)12
Interfacing Between LVDS and ECLAN1568/D (121.0kB)11
Interfacing with ECLinPSAND8066/D (72kB)3
Metastability and the ECLinPS FamilyAN1504/D (103.0kB)3
Odd Number Divide By Counters with 50% Outputs and Synchronous ClocksAND8001/D (90.0kB)0
Phase Lock Loop General OperationsAND8040/D (64.0kB)3
Storage and Handling of Drypack Surface Mount DeviceAND8003/D (49kB)2Mar, 2016
Termination of ECL Logic DevicesAND8020/D (176.0kB)6
The ECL Translator GuideAN1672/D (142.0kB)12
Thermal Analysis and Reliability of WIRE BONDED ECLAND8072/D (119.0kB)5
Using Wire-OR Ties in ECLInPS™ DesignsAN1650/D (1130.0kB)3
Data Sheets (1)
Document TitleDocument ID/SizeRevisionRevision Date
5V ECL 2-Input Differential AND/NANDMC10EL05/D (164kB)7Jul, 2016
Simulation Models (2)
Document TitleDocument ID/SizeRevisionRevision Date
IBIS Model for mc10el05d -5.0VMC10EL05D_-50.IBS (10.0kB)1
IBIS Model for mc10el05d 5.0VMC10EL05D_50.IBS (10.0kB)1
Package Drawings (2)
Document TitleDocument ID/SizeRevision
SOIC-8 Narrow Body751-07 (62.6kB)AK
TSSOP 8 3.0x3.0x0.95 mm948R-02 (77.3kB)A
Order Information
ProductStatusCompliancePackageMSL*ContainerBudgetary Price/Unit
MC10EL05DGActivePb-free Halide freeSOIC-8751-071Tube98Contact BDTIC
MC10EL05DR2GActivePb-free Halide freeSOIC-8751-071Tape and Reel2500Contact BDTIC
MC10EL05DTGLast ShipmentsPb-free Halide freeTSSOP-8948R-023Tube100
Specifications
ProductTypeChannelsInput LevelOutput LevelVCC Typ (V)fToggle Max (MHz)tpd Typ (ns)tJitter Typ (ps)tR & tF Max (ps)
MC10EL05DGAND/NAND1ECLECL520000.2751350
MC10EL05DR2GAND/NAND1ECLECL520000.2751350
5V ECL 2-Input Differential AND/NAND (164kB) MC10EL05
AC Characteristics of ECL Devices NB100LVEP91
Clock Generation and Clock and Data Marking and Ordering Information Guide NB100LVEP91
Clock Management Design Using Low Skew and Low Jitter Devices MC10H604
Designing with PECL (ECL at +5.0 V) NB100LVEP91
ECL Clock Distribution Techniques NB100LVEP91
ECLinPS and ECLinPS Lite SPICE I/O Modeling Kit MC100EP91
ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information Guide NB100LVEP91
Interfacing Between LVDS and ECL NB100ELT23L
Interfacing with ECLinPS NB100LVEP91
Metastability and the ECLinPS Family MC10EPT20
Odd Number Divide By Counters with 50% Outputs and Synchronous Clocks NUP4201
Phase Lock Loop General Operations MC10H604
Storage and Handling of Drypack Surface Mount Device NB3U23C
Termination of ECL Logic Devices NB100LVEP91
The ECL Translator Guide NB100LVEP91
Thermal Analysis and Reliability of WIRE BONDED ECL NB100LVEP91
Using Wire-OR Ties in ECLInPS™ Designs MC10H351
IBIS Model for mc10el05d -5.0V MC10EL05
IBIS Model for mc10el05d 5.0V MC10EL05
SOIC-8 Narrow Body CM1216
TSSOP 8 3.0x3.0x0.95 mm NB100ELT23L
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