MC10EP57: Multiplexer, 4:1 Differential, ECL, 3.3 V / 5.0 V

The MC10/100EP57 is a fully differential 4:1 multiplexer. By leaving the SEL1 line open (pulled LOW via the input pulldown resistors) the device can also be used as a differential 2:1 multiplexer with SEL0 input selecting between D0 and D1. The fully differential architecture of the EP57 makes it ideal for use in low skew applications such as clock distribution.The SEL1 is the most significant select line. The binary number applied to the select inputs will select the same numbered data input (i.e., 00 selects D0).Multiple VBB outputs are provided. The VBB pin, an internally generated voltage supply, is available to this device only. For single-ended input conditions, the unused differential input is connected to VBB as a switching reference voltage. VBB may also rebias AC coupled inputs. When used, decouple VBB and VCC via a 0.01 uF capacitor and limit current sourcing or sinking to 0.5mA. When not used, VBB should be left open.The 100 Series contains temperature compensation.

Features
  • 375 ps Typical Propagation Delays
  • Maximum Frequency > 2 GHz Typical
  • PECL Mode Operating Range: VCC = 3.0 V to 5.5 V with VEE = 0 V
  • NECL Mode Operating Range: VCC = 0 V with VEE = -3.0 V to -5.5 V
  • Open Input Default State
  • Safety Clamp on Inputs
  • Q Output will default LOW with inputs open or at VEE
  • VBB Outputs
  • Useful as Either 4:1 or 2:1 Multiplexer
  • These are Pb-Free Devices
Applications
  • Ideal for use in low skew applications such as clock distribution
Application Notes (16)
Document TitleDocument ID/SizeRevisionRevision Date
AC Characteristics of ECL DevicesAND8090/D (896.0kB)1
Clock Generation and Clock and Data Marking and Ordering Information GuideAND8002/D (71kB)12
Designing with PECL (ECL at +5.0 V)AN1406/D (105.0kB)2
ECL Clock Distribution TechniquesAN1405/D (54.0kB)1
ECLinPS Plus™ Spice Modeling KitAND8009/D (343.0kB)11
ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information GuideAND8002 (71kB)12
Interfacing Between LVDS and ECLAN1568/D (121.0kB)11
Interfacing with ECLinPSAND8066/D (72kB)3
Metastability and the ECLinPS FamilyAN1504/D (103.0kB)3
Odd Number Divide By Counters with 50% Outputs and Synchronous ClocksAND8001/D (90.0kB)0
Phase Lock Loop General OperationsAND8040/D (64.0kB)3
Storage and Handling of Drypack Surface Mount DeviceAND8003/D (49kB)2Mar, 2016
Termination of ECL Logic DevicesAND8020/D (176.0kB)6
The ECL Translator GuideAN1672/D (142.0kB)12
Thermal Analysis and Reliability of WIRE BONDED ECLAND8072/D (119.0kB)5
Using Wire-OR Ties in ECLInPS™ DesignsAN1650/D (1130.0kB)3
Data Sheets (1)
Document TitleDocument ID/SizeRevisionRevision Date
3.3V/5V ECL 4:1 Differential MultiplexerMC10EP57/D (107kB)13
Simulation Models (4)
Document TitleDocument ID/SizeRevisionRevision Date
IBIS Model for MC10EP57DT -3.3VMC10EP57DT_-33.IBS (12.0kB)4
IBIS Model for MC10EP57DT -5.2VMC10EP57DT_-52.IBS (12.0kB)4
IBIS Model for MC10EP57DT 3.3VMC10EP57DT_33.IBS (11.0kB)3
IBIS Model for MC10EP57DT for 5.0VMC10EP57DT_50.IBS (12.0kB)3
Package Drawings (2)
Document TitleDocument ID/SizeRevision
QFN20, 4x4, 0.5P485E-01 (60.9kB)B
TSSOP-20 WB948E-02 (39.7kB)D
Order Information
ProductStatusCompliancePackageMSL*ContainerBudgetary Price/Unit
MC10EP57DTGActivePb-free Halide freeTSSOP-20948E-021Tube75Contact BDTIC
MC10EP57DTR2GActivePb-free Halide freeTSSOP-20948E-021Tape and Reel2500Contact BDTIC
MC10EP57MNGActivePb-free Halide freeQFN-20485E-011Tube92Contact BDTIC
MC10EP57MNTXGLifetimePb-free Halide freeQFN-20485E-011Tape and Reel3000
Specifications
ProductInput/Output RatioChannelsInput LevelOutput LevelVCC Typ (V)fMax Typ (MHz)tJitter Typ (ps)tskew(OO) Max (ps)tpd Typ (ns)
MC10EP57DTG4:11CML ECLECL5 3.330000.1352000.375
MC10EP57DTR2G4:11CML ECLECL5 3.330000.1352000.375
MC10EP57MNG4:11ECL CMLECL3.3 530000.1352000.375
3.3V/5V ECL 4:1 Differential Multiplexer (107kB) MC10EP57
AC Characteristics of ECL Devices NB100LVEP91
Clock Generation and Clock and Data Marking and Ordering Information Guide NB100LVEP91
Designing with PECL (ECL at +5.0 V) NB100LVEP91
ECL Clock Distribution Techniques NB100LVEP91
ECLinPS Plus™ Spice Modeling Kit MC10EPT20
ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information Guide NB100LVEP91
Interfacing Between LVDS and ECL NB100ELT23L
Interfacing with ECLinPS NB100LVEP91
Metastability and the ECLinPS Family MC10EPT20
Odd Number Divide By Counters with 50% Outputs and Synchronous Clocks NUP4201
Phase Lock Loop General Operations MC10H604
Storage and Handling of Drypack Surface Mount Device NB3U23C
Termination of ECL Logic Devices NB100LVEP91
The ECL Translator Guide NB100LVEP91
Thermal Analysis and Reliability of WIRE BONDED ECL NB100LVEP91
Using Wire-OR Ties in ECLInPS™ Designs MC10H351
IBIS Model for MC10EP57DT -3.3V MC10EP57
IBIS Model for MC10EP57DT -5.2V MC10EP57
IBIS Model for MC10EP57DT 3.3V MC10EP57
IBIS Model for MC10EP57DT for 5.0V MC10EP57
TSSOP-20 WB NLSX3018
QFN20, 4x4, 0.5P MC10EP57