MC10EP89: Coaxial Cable Driver

The MC10EP89 is a differential fanout gate specifically designed to drive coaxial cables. The device is especially useful in digital video broadcasting applications; for this application, since the system is polarity free, each output can be used as an independent driver. The driver produces swings 70% larger than a standard ECL output. When driving a coaxial cable, proper termination is required at both ends of the line to minimize signal loss. The 1.6 V (5 V) and 1.4 V (3.3 V) swing allow for termination at both ends of the cable, while maintaining a 800 mV (5 V) and 700 mV (3.3 V) swing at the receiving end of the cable. Because of the larger output swings, the device cannot be terminated into the standard VCC-2.0 V. All of the DC parameters are tested with a 50 ohms to VCC-3.0 V load. The driver accepts a standard differential ECL input and can run off of the digital video broadcast standard -5.0 V supply.

Features
  • 310ps Typical Propagation Delay
  • Maximum Frequency > 2 Ghz Typical
  • 1.6V (5V) and 1.4V (3.3V) VOUTpp Swing
  • PECL Mode Operating Range: VCC= 3.0 V to 5.5 V with VEE= 0 V
  • NECL Mode Operating Range: VCC= 0 V with VEE= -3.0 V to -5.5 V
  • Open Input Default State
  • Safety Clamp on Inputs
  • Q Output will default LOW with inputs open or at VEE
  • Pb-Free Packages are Available
Application Notes (16)
Document TitleDocument ID/SizeRevisionRevision Date
AC Characteristics of ECL DevicesAND8090/D (896.0kB)1
Clock Generation and Clock and Data Marking and Ordering Information GuideAND8002/D (71kB)12
Designing with PECL (ECL at +5.0 V)AN1406/D (105.0kB)2
ECL Clock Distribution TechniquesAN1405/D (54.0kB)1
ECLinPS Plus™ Spice Modeling KitAND8009/D (343.0kB)11
ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information GuideAND8002 (71kB)12
Interfacing Between LVDS and ECLAN1568/D (121.0kB)11
Interfacing with ECLinPSAND8066/D (72kB)3
Metastability and the ECLinPS FamilyAN1504/D (103.0kB)3
Odd Number Divide By Counters with 50% Outputs and Synchronous ClocksAND8001/D (90.0kB)0
Phase Lock Loop General OperationsAND8040/D (64.0kB)3
Storage and Handling of Drypack Surface Mount DeviceAND8003/D (49kB)2Mar, 2016
Termination of ECL Logic DevicesAND8020/D (176.0kB)6
The ECL Translator GuideAN1672/D (142.0kB)12
Thermal Analysis and Reliability of WIRE BONDED ECLAND8072/D (119.0kB)5
Using Wire-OR Ties in ECLInPS™ DesignsAN1650/D (1130.0kB)3
Data Sheets (1)
Document TitleDocument ID/SizeRevisionRevision Date
3.3V / 5V ECL Coaxial Cable DriverMC10EP89/D (114.0kB)7
Simulation Models (4)
Document TitleDocument ID/SizeRevisionRevision Date
IBIS Model for MC10EP89D for VCC 3.3 VMC10EP89D_33.IBS (6.0kB)2
IBIS Model for MC10EP89D for VCC 5.0 VMC10EP89D_50.IBS (6.0kB)2
IBIS Model for MC10EP89D for VEE -3.3 VMC10EP89D_-33.IBS (6.0kB)2
IBIS Model for MC10EP89D for VEE -5.2 VMC10EP89D_-52.IBS (6.0kB)2
Package Drawings (3)
Document TitleDocument ID/SizeRevision
DFN8 2.0x2.0x0.9mm, 0.5p506AA (31.8kB)F
SOIC-8 Narrow Body751-07 (62.6kB)AK
TSSOP 8 3.0x3.0x0.95 mm948R-02 (77.3kB)A
Order Information
ProductStatusCompliancePackageMSL*ContainerBudgetary Price/Unit
MC10EP89DGActivePb-free Halide freeSOIC-8751-071Tube98Contact BDTIC
MC10EP89DR2GActivePb-free Halide freeSOIC-8751-071Tape and Reel2500Contact BDTIC
MC10EP89DTGActivePb-free Halide freeTSSOP-8948R-023Tube100Contact BDTIC
MC10EP89DTR2GActivePb-free Halide freeTSSOP-8948R-023Tape and Reel2500Contact BDTIC
MC10EP89MNR4GLifetimePb-free Halide freeDFN-8506AA1Tape and Reel1000
Specifications
ProductTypeChannelsInput / Output RatioInput LevelOutput LevelVCC Typ (V)tJitterRMS Typ (ps)tskew(o-o) Max (ps)tpd Typ (ns)tR & tF Max (ps)fmaxClock Typ (MHz)fmaxData Typ (Mbps)
MC10EP89DGCoaxial Cable Driver11:2ECL CML2X ECL5 3.30.5200.313252000
MC10EP89DR2GCoaxial Cable Driver11:2ECL CML2X ECL3.3 50.5200.313252000
MC10EP89DTGCoaxial Cable Driver11:2ECL CML2X ECL5 3.30.5200.313252000
MC10EP89DTR2GCoaxial Cable Driver11:2ECL CML2X ECL5 3.30.5200.313252000
3.3V / 5V ECL Coaxial Cable Driver (114.0kB) MC10EP89
AC Characteristics of ECL Devices NB100LVEP91
Clock Generation and Clock and Data Marking and Ordering Information Guide NB100LVEP91
Designing with PECL (ECL at +5.0 V) NB100LVEP91
ECL Clock Distribution Techniques NB100LVEP91
ECLinPS Plus™ Spice Modeling Kit MC10EPT20
ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information Guide NB100LVEP91
Interfacing Between LVDS and ECL NB100ELT23L
Interfacing with ECLinPS NB100LVEP91
Metastability and the ECLinPS Family MC10EPT20
Odd Number Divide By Counters with 50% Outputs and Synchronous Clocks NUP4201
Phase Lock Loop General Operations MC10H604
Storage and Handling of Drypack Surface Mount Device NB3U23C
Termination of ECL Logic Devices NB100LVEP91
The ECL Translator Guide NB100LVEP91
Thermal Analysis and Reliability of WIRE BONDED ECL NB100LVEP91
Using Wire-OR Ties in ECLInPS™ Designs MC10H351
IBIS Model for MC10EP89D for VCC 3.3 V MC10EP89
IBIS Model for MC10EP89D for VCC 5.0 V MC10EP89
IBIS Model for MC10EP89D for VEE -3.3 V MC10EP89
IBIS Model for MC10EP89D for VEE -5.2 V MC10EP89
SOIC-8 Narrow Body CM1216
TSSOP 8 3.0x3.0x0.95 mm NB100ELT23L
DFN8 2.0x2.0x0.9mm, 0.5p NUF4220
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