MC10EP90: Translator, Triple ECL Input to LVPECL / PECL Output

The MC10/100EP90 is a TRIPLE ECL TO LVPECL/PECL translator. The device receives differential LVECL or ECL signals and translates them to differential LVPECL or PECL output signals. A VBB output is provided for interfacing with single ended LVECL or ECL signals at the input. If a single ended input is to be used the VBB output should be connected to the D input. The active signal would then drive the D input. When used the VBB output should be bypassed to ground by a 0.01 F capacitor. The VBB output is designed to act as the switching reference for the EP90 under single ended input switching conditions, as a result this pin can only source/sink up to 0.5mA of current. To accomplish the level translation the EP90 requires three power rails. The VCC supply should be connected to the positive supply, and the VEE connected to the negative supply. The 100 Series contains temperature compensation.

Features

260 ps Typical Propagation Delay
Maximum Frequency > 3 GHz Typical
Voltage Supplies VCC = 3.0 V to 5.5 V, VEE = -3.0 V to -5.5 V, GND = 0 V
Open Input Default State
Safety Clamp on Inputs
Fully Differential Design
Q Output will default LOW with inputs open or at VEE
VBB Output
These are Pb-Free Devices

Application Notes (10)

Document Title	Document ID/Size	Revision
AC Characteristics of ECL Devices	AND8090/D (896.0kB)	1
Clock Generation and Clock and Data Marking and Ordering Information Guide	AND8002/D (71kB)	12
Designing with PECL (ECL at +5.0 V)	AN1406/D (105.0kB)	2
ECL Clock Distribution Techniques	AN1405/D (54.0kB)	1
ECLinPS Plus™ Spice Modeling Kit	AND8009/D (343.0kB)	11
Interfacing Between LVDS and ECL	AN1568/D (121.0kB)	11
Interfacing with ECLinPS	AND8066/D (72kB)	3
Odd Number Divide By Counters with 50% Outputs and Synchronous Clocks	AND8001/D (90.0kB)	0
Termination of ECL Logic Devices	AND8020/D (176.0kB)	6
The ECL Translator Guide	AN1672/D (142.0kB)	12