MC10EPT20: Translator, LVTTL / LVCMOS to Differential LVPECL

The MC10EPT20 is a 3.3 V TTL/CMOS to differential PECL translator. Because PECL (Positive ECL) levels are used, only +3.3 V and ground are required. The small outline SOIC-8 package and the single gate of the EPT20 makes it ideal for those applications where space, performance, and low power are at a premium.

Features
  • 390ps Typical Propagation Delay
  • Maximum Frequency > 1 Ghz Typical
  • PNP TTL Inputs for Minimal Loading
  • Operating Range V CC = 3.0V to 3.6V with GND = 0
  • Q Output will default HIGH with inputs open
Applications
  • Precision Clock Translation
Application Notes (16)
Document TitleDocument ID/SizeRevisionRevision Date
AC Characteristics of ECL DevicesAND8090/D (896.0kB)1
Clock Generation and Clock and Data Marking and Ordering Information GuideAND8002/D (71kB)12
Designing with PECL (ECL at +5.0 V)AN1406/D (105.0kB)2
ECL Clock Distribution TechniquesAN1405/D (54.0kB)1
ECLinPS Plus™ Spice Modeling KitAND8009/D (343.0kB)11
ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information GuideAND8002 (71kB)12
EPT Spice Modeling KitAND8014/D (63.0kB)0
Interfacing with ECLinPSAND8066/D (72kB)3
Metastability and the ECLinPS FamilyAN1504/D (103.0kB)3
Odd Number Divide By Counters with 50% Outputs and Synchronous ClocksAND8001/D (90.0kB)0
Phase Lock Loop General OperationsAND8040/D (64.0kB)3
Storage and Handling of Drypack Surface Mount DeviceAND8003/D (49kB)2Mar, 2016
Termination of ECL Logic DevicesAND8020/D (176.0kB)6
The ECL Translator GuideAN1672/D (142.0kB)12
Thermal Analysis and Reliability of WIRE BONDED ECLAND8072/D (119.0kB)5
Using Wire-OR Ties in ECLInPS™ DesignsAN1650/D (1130.0kB)3
Data Sheets (1)
Document TitleDocument ID/SizeRevisionRevision Date
3.3 V LVTTL/LVCMOS to Differential LVPECL TranslatorMC10EPT20/D (162kB)12Aug, 2016
Simulation Models (1)
Document TitleDocument ID/SizeRevisionRevision Date
IBIS Model for MC10EPT20DMC10EPT20D_33.IBS (5.0kB)1
Package Drawings (3)
Document TitleDocument ID/SizeRevision
DFN8 2.0x2.0x0.9mm, 0.5p506AA (31.8kB)F
SOIC-8 Narrow Body751-07 (62.6kB)AK
TSSOP 8 3.0x3.0x0.95 mm948R-02 (77.3kB)A
Order Information
ProductStatusCompliancePackageMSL*ContainerBudgetary Price/Unit
MC10EPT20DGActivePb-free Halide freeSOIC-8751-071Tube98Contact BDTIC
MC10EPT20DR2GActivePb-free Halide freeSOIC-8751-071Tape and Reel2500Contact BDTIC
MC10EPT20DTGActivePb-free Halide freeTSSOP-8948R-023Tube100Contact BDTIC
MC10EPT20DTR2GActivePb-free Halide freeTSSOP-8948R-023Tape and Reel2500Contact BDTIC
MC10EPT20MNR4GLifetimePb-free Halide freeDFN-8506AA1Tape and Reel1000
Specifications
ProductChannelsInput LevelOutput LevelVCC Typ (V)fMax Typ (MHz)tpd Typ (ns)tR & tF Max (ps)
MC10EPT20DG1TTL CMOSECL3.310000.37170
MC10EPT20DR2G1CMOS TTLECL3.310000.37170
MC10EPT20DTG1CMOS TTLECL3.310000.37170
MC10EPT20DTR2G1CMOS TTLECL3.310000.37170
3.3 V LVTTL/LVCMOS to Differential LVPECL Translator (162kB) MC10EPT20
AC Characteristics of ECL Devices NB100LVEP91
Clock Generation and Clock and Data Marking and Ordering Information Guide NB100LVEP91
Designing with PECL (ECL at +5.0 V) NB100LVEP91
ECL Clock Distribution Techniques NB100LVEP91
ECLinPS Plus™ Spice Modeling Kit MC10EPT20
ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information Guide NB100LVEP91
EPT Spice Modeling Kit MC10EPT20
Interfacing with ECLinPS NB100LVEP91
Metastability and the ECLinPS Family MC10EPT20
Odd Number Divide By Counters with 50% Outputs and Synchronous Clocks NUP4201
Phase Lock Loop General Operations MC10H604
Storage and Handling of Drypack Surface Mount Device NB3U23C
Termination of ECL Logic Devices NB100LVEP91
The ECL Translator Guide NB100LVEP91
Thermal Analysis and Reliability of WIRE BONDED ECL NB100LVEP91
Using Wire-OR Ties in ECLInPS™ Designs MC10H351
IBIS Model for MC10EPT20D MC10EPT20
SOIC-8 Narrow Body CM1216
TSSOP 8 3.0x3.0x0.95 mm NB100ELT23L
DFN8 2.0x2.0x0.9mm, 0.5p NUF4220