MC10H104: Quad 2-Input AND Gate

The MC10H104 is a quad 2-input AND gate. One of the gates has both AND/NAND outputs available. This MECL 10H part is a functional/pinout duplication of the standard MECL 10K family part, with 100% improvement in propagation delay, and no increase in power- supply current.

Features
  • Power Dissipation 25 mW/Gate (same as MECL 10K)
  • Improved Noise Margin 150 mV (Over Operating Voltage and Temperature Range)
  • Voltage Compensated
  • MECL 10K-Compatible
  • Propagation Delay, 1.0 ns Typical
  • Pb-Free Packages are Available
Application Notes (16)
Document TitleDocument ID/SizeRevisionRevision Date
AC Characteristics of ECL DevicesAND8090/D (896.0kB)1
Clock Generation and Clock and Data Marking and Ordering Information GuideAND8002/D (71kB)12
Clock Management Design Using Low Skew and Low Jitter DevicesTND301/D (205.0kB)0
Designing with PECL (ECL at +5.0 V)AN1406/D (105.0kB)2
ECL Clock Distribution TechniquesAN1405/D (54.0kB)1
ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information GuideAND8002 (71kB)12
Family Characteristics for MECL 10H™ and MECL 10K™TND309/D (248.0kB)1
Interfacing Between LVDS and ECLAN1568/D (121.0kB)11
Interfacing with ECLinPSAND8066/D (72kB)3
Odd Number Divide By Counters with 50% Outputs and Synchronous ClocksAND8001/D (90.0kB)0
Phase Lock Loop General OperationsAND8040/D (64.0kB)3
Storage and Handling of Drypack Surface Mount DeviceAND8003/D (49kB)2Mar, 2016
Termination of ECL Logic DevicesAND8020/D (176.0kB)6
The ECL Translator GuideAN1672/D (142.0kB)12
Thermal Analysis and Reliability of WIRE BONDED ECLAND8072/D (119.0kB)5
Using Wire-OR Ties in ECLInPS™ DesignsAN1650/D (1130.0kB)3
Data Sheets (1)
Document TitleDocument ID/SizeRevisionRevision Date
Quad 2-Input AND GateMC10H104/D (134kB)9Aug, 2016
Simulation Models (3)
Document TitleDocument ID/SizeRevisionRevision Date
IBIS Model for MC10H104LMC10H104L.IBS (6.0kB)0
IBIS Model for MC10H104PMC10H104P.IBS (6.0kB)0
MECL 10H SPICE Kit for Berkeley SPICE (PSPICE)AN1578/D (161.0kB)0
Package Drawings (2)
Document TitleDocument ID/SizeRevision
20 LEAD PLLC775-02 (60.9kB)F
PDIP-16648-08 (34.2kB)V
Order Information
ProductStatusCompliancePackageMSL*ContainerBudgetary Price/Unit
MC10H104FNGActivePb-free Halide freePLLC-20775-023Tube46Contact BDTIC
MC10H104FNR2GActivePb-free Halide freePLLC-20775-023Tape and Reel500Contact BDTIC
MC10H104PGActivePb-free Halide freePDIP-16648-08NATube25Contact BDTIC
Specifications
ProductTypeChannelsInput LevelOutput LevelVCC Typ (V)fToggle Max (MHz)tpd Typ (ns)tJitter Typ (ps)tR & tF Max (ps)
MC10H104FNGAND4ECLECL-5.211600
MC10H104FNR2GAND4ECLECL-5.211600
MC10H104PGAND4ECLECL-5.211600
Quad 2-Input AND Gate (134kB) MC10H104
AC Characteristics of ECL Devices NB100LVEP91
Clock Generation and Clock and Data Marking and Ordering Information Guide NB100LVEP91
Clock Management Design Using Low Skew and Low Jitter Devices MC10H604
Designing with PECL (ECL at +5.0 V) NB100LVEP91
ECL Clock Distribution Techniques NB100LVEP91
ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information Guide NB100LVEP91
Family Characteristics for MECL 10H™ and MECL 10K™ MC10H604
Interfacing Between LVDS and ECL NB100ELT23L
Interfacing with ECLinPS NB100LVEP91
Odd Number Divide By Counters with 50% Outputs and Synchronous Clocks NUP4201
Phase Lock Loop General Operations MC10H604
Storage and Handling of Drypack Surface Mount Device NB3U23C
Termination of ECL Logic Devices NB100LVEP91
The ECL Translator Guide NB100LVEP91
Thermal Analysis and Reliability of WIRE BONDED ECL NB100LVEP91
Using Wire-OR Ties in ECLInPS™ Designs MC10H351
IBIS Model for MC10H104L MC10H104
IBIS Model for MC10H104P MC10H104
MECL 10H SPICE Kit for Berkeley SPICE (PSPICE) MC100LVEL56
20 LEAD PLLC MC10H351
PDIP-16 MC10H350
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